Abstract:
An integrated semiconductor with lateral thermal insulation is disclosed. In one embodiment, the chip has, on a common substrate, at least one power semiconductor circuit region and, laterally adjacent to the power semiconductor circuit region, at least one further temperature-sensitive semiconductor circuit region, interspaces being maintained between the circuit regions. At least one thermally insulating trench is provided at least in each interspace in each case between power semiconductor circuit region(s) and temperature-sensitive semiconductor circuit region(s), which at least one thermally insulating trench extends into the depth of the chip right into the substrate and in the longitudinal direction of the chip at least over a lateral side of the at least one power semiconductor circuit region and/or the temperature-sensitive semiconductor circuit region and is either unfilled or filled with a thermally insulating filling material.
Abstract:
An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.
Abstract:
A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy.
Abstract:
An integrated semiconductor with lateral thermal insulation is disclosed. In one embodiment, the chip has, on a common substrate, at least one power semiconductor circuit region and, laterally adjacent to the power semiconductor circuit region, at least one further temperature-sensitive semiconductor circuit region, interspaces being maintained between the circuit regions. At least one thermally insulating trench is provided at least in each interspace in each case between power semiconductor circuit region(s) and temperature-sensitive semiconductor circuit region(s), which at least one thermally insulating trench extends into the depth of the chip right into the substrate and in the longitudinal direction of the chip at least over a lateral side of the at least one power semiconductor circuit region and/or the temperature-sensitive semiconductor circuit region and is either unfilled or filled with a thermally insulating filling material.
Abstract:
Semiconductor components having a semiconductor body which includes a semiconductor base surface have to be sealed with a molding compound in order to protect against moisture or heat. Mechanical interlocking of the molding compound to the semiconductor base surface is achieved by means of at least one interlocking structure. This may be either a horizontal interlocking structure for mechanically interlocking the molding compound to the semiconductor base surface in the direction which is horizontal with respect to the semiconductor base surface and/or a vertical interlocking structure for mechanically interlocking the molding compound to the semiconductor base surface in the direction which is vertical with respect to the semiconductor base surface.
Abstract:
A method for fabricating an integrated electronic circuit includes producing electrically active elements in the region of one plane. At least one insulation layer and at least one contact-making layer are applied on the electrically active elements, and subsequently at least one connecting wire is applied to the contact-making layer. The contact-making layer is produced in such a way that the contact-making layer has a thickness which is at least 10% of the radius of the connecting wire. An integrated electronic circuit is fabricated with the aid of the method.
Abstract:
An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.
Abstract:
A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.
Abstract:
A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the side edges, the rear side and the top side, on which surface-mountable external contacts are arranged. One embodiment includes power semiconductor components, wherein the metallic coating connects a rear side electrode to one of the surface-mountable external contacts on the top side of a power semiconductor chip.
Abstract:
An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.