公开(公告)号：US08802499B2

公开(公告)日：2014-08-12

申请号：US13678026

申请日：2012-11-15

申请人： Michael G. Kelly ,  David Jon Hiner ,  Ronald Patrick Huemoeller

发明人： Michael G. Kelly ,  David Jon Hiner ,  Ronald Patrick Huemoeller

IPC分类号： H01L21/00

CPC分类号： H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L22/14 ,  H01L22/20 ,  H01L23/04 ,  H01L23/147 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81908 ,  H01L2224/81986 ,  H01L2224/83192 ,  H01L2224/83908 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/00

摘要： Methods for temporary wafer molding for chip-on-wafer assembly may include bonding one or more semiconductor die to an interposer wafer, applying a temporary mold material to encapsulate the bonded die, and backside processing the interposer, which may be singulated to generate assemblies comprising the bonded die, the interposer die, which may be bonded to packaging substrates. The temporary mold material may be removed and the bonded die may be tested. Additional die may be bonded to the assemblies based on the electrical testing. The interposer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The backside processing may comprise thinning the interposer wafer to expose through-silicon-vias (TSVs) and placing metal contacts on the exposed TSVs. The die may be bonded to the interposer utilizing a mass reflow or thermal compression process.

摘要翻译： 用于片上晶片组装的临时晶片成型的方法可以包括将一个或多个半导体管芯接合到插入器晶片，施加临时模制材料以封装接合的管芯，以及背面处理插入件，其可以被单个化以产生组件， 可以粘合到封装衬底上的粘合模，插入模。 可以移除临时模具材料并且可以测试粘合的模具。 基于电气测试，附加模具可以结合到组件。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器。 背面处理可以包括使内插器晶片变薄以暴露穿过硅通孔（TSV）并且将金属触点放置在暴露的TSV上。 可以使用质量回流或热压缩工艺将管芯结合到插入件。

公开(公告)号：US08432022B1

公开(公告)日：2013-04-30

申请号：US12569300

申请日：2009-09-29

申请人： Ronald Patrick Huemoeller ,  Brett Dunlap ,  David Jon Hiner

发明人： Ronald Patrick Huemoeller ,  Brett Dunlap ,  David Jon Hiner

IPC分类号： H01L23/552 ,  H01L21/70

CPC分类号： H01L23/552 ,  H01L21/70 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331

摘要： A shielded embedded electronic component substrate includes a core dielectric layer having a die opening. An electrically conductive die shield lines the die opening. An electronic component is mounted within the die opening and to the die shield, where the die shield shields the electronic component. By mounting the electronic component within the die opening, the shielded embedded electronic component substrate is made relatively thin. Further, heat generated by the electronic component is dissipated to the die shield and to the ambient environment. Accordingly, the shielded embedded electronic component substrate is well suited for use when the electronic component generates a significant amount of heat, e.g., in high power applications.

摘要翻译： 屏蔽嵌入式电子元件基板包括具有模具开口的芯介质层。 导电模具屏蔽线使模具开口线对准。 电子部件安装在模具开口内和模具屏蔽件之间，其中模具屏蔽罩屏蔽电子部件。 通过将电子部件安装在模具开口内，屏蔽的嵌入式电子部件基板被制成相对较薄。 此外，由电子部件产生的热量被散发到模具屏蔽件和周围环境。 因此，当电子部件产生大量的热量时，例如在大功率应用中，屏蔽的嵌入式电子部件基板非常适用于使用。

公开(公告)号：US08390130B1

公开(公告)日：2013-03-05

申请号：US12985888

申请日：2011-01-06

申请人： David Jon Hiner ,  Ronald Patrick Huemoeller ,  Michael G. Kelly

发明人： David Jon Hiner ,  Ronald Patrick Huemoeller ,  Michael G. Kelly

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/6836 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/05552

摘要： A stacked assembly includes a stacked structure stacked on a through via recessed reveal structure. The through via recessed reveal structure includes recesses within a backside surface of an electronic component that expose backsides of through vias. Pillars of the stacked structure are attached to the exposed backsides of the through vias through the recesses. The recesses in combination with the pillars work as a lock and key arrangement to insure self-alignment of the pillars with the backsides of the through vias allowing fine pitch interconnections to be realized. Further, by forming the interconnections to the backsides of the through vias within the recesses, the overall thickness of the stacked assembly is minimized. Further still, by forming the interconnections to the backsides of the through vias within the recesses, shorting between adjacent through vias is minimized or eliminated.

公开(公告)号：US08316536B1

公开(公告)日：2012-11-27

申请号：US12151857

申请日：2008-05-09

申请人： Ronald Patrick Huemoeller ,  David Jon Hiner ,  Russ Lie

发明人： Ronald Patrick Huemoeller ,  David Jon Hiner ,  Russ Lie

IPC分类号： H01K3/10

CPC分类号： H01L24/73 ,  H01L21/4857 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/1815 ,  H05K1/056 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/423 ,  H05K7/1061 ,  H05K2201/09036 ,  H05K2201/09554 ,  H05K2203/0723 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of making a semiconductor package substrate includes laser-ablating channels in the substrate. After the channels are ablated in the substrate, conductive material is added to fill the channels and cover the surface of the substrate. Then a photomask etching process simultaneously forms a circuit pattern above the surface of the substrate and removes excess metal above the channels, by removing metal above the surface only in patterned regions. The result is a two-level circuit pattern having conductors within and above the substrate.

摘要翻译： 制造半导体封装衬底的方法包括在衬底中的激光烧蚀通道。 在衬底中消融通道之后，加入导电材料以填充通道并覆盖衬底的表面。 然后，光掩模蚀刻工艺同时在衬底的表面上形成电路图案，并且通过仅在图案化区域中去除表面上方的金属，去除通道上方的多余金属。 结果是在衬底内和上方具有导体的两电平电路图案。

公开(公告)号：US09136159B2

公开(公告)日：2015-09-15

申请号：US13678058

申请日：2012-11-15

申请人： Michael G. Kelly ,  Ronald Patrick Huemoeller ,  Won Chul Do ,  David Jon Hiner

发明人： Michael G. Kelly ,  Ronald Patrick Huemoeller ,  Won Chul Do ,  David Jon Hiner

IPC分类号： H01L21/762 ,  H01L23/14 ,  H01L21/48 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L21/76251 ,  H01L21/486 ,  H01L21/50 ,  H01L21/563 ,  H01L21/67288 ,  H01L21/6836 ,  H01L21/6838 ,  H01L21/68735 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5386 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68322 ,  H01L2223/54486 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27622 ,  H01L2224/2763 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81

摘要： Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. The additional die may comprise electronic devices. The first semiconductor die may comprise an interposer die or may comprise electronic devices. The first semiconductor die may be bonded to the packaging substrate utilizing a mass reflow process or a thermal compression process. The additional die may be bonded to the first die utilizing a mass reflow process or a thermal compression process. The bonded die may be encapsulated in a mold material, which may comprise a polymer. The one or more additional die may comprise micro-bumps for coupling to the first semiconductor die.

摘要翻译： 公开了具有管芯到基板的第一接合的半导体器件封装的方法和系统，并且可以包括将第一半导体管芯接合到封装基板，在第一半导体管芯和封装基板之间施加底部填充材料， 或更多的额外管芯到第一半导体管芯。 附加的管芯可以包括电子器件。 第一半导体管芯可以包括插入器管芯，或者可以包括电子器件。 第一半导体管芯可以利用质量回流工艺或热压缩工艺结合到封装衬底上。 可以使用质量回流工艺或热压缩工艺将附加模具结合到第一模具。 粘合的模具可以包封在可以包含聚合物的模具材料中。 一个或多个附加管芯可以包括用于耦合到第一半导体管芯的微突起。

公开(公告)号：US08872329B1

公开(公告)日：2014-10-28

申请号：US12351596

申请日：2009-01-09

申请人： David Jon Hiner ,  Ronald Patrick Huemoeller

发明人： David Jon Hiner ,  Ronald Patrick Huemoeller

IPC分类号： H01L23/12

CPC分类号： H05K3/4617 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/48 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H05K3/0064 ,  H05K2203/041 ,  H05K2203/061 ,  H05K2203/0703 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00

摘要： An extended landing pad substrate package includes a dielectric layer having an upper surface and an opposite lower surface. A lower circuit pattern is embedded in the lower surface of the dielectric layer. The lower circuit pattern includes traces having a first thickness and extended landing pads having a second thickness greater than the first thickness. Blind via apertures are formed through an upper circuit pattern embedded into the upper surface of the dielectric layer, through the dielectric layer and to the extended landing pads. The length of the blind via apertures is minimized due to the increase second thickness of the extended landing pads as compared to the first thickness of traces. Accordingly, the width of the blind via apertures at the upper surface of the dielectric layer is minimized.

摘要翻译： 延伸的着陆垫衬底封装包括具有上表面和相对的下表面的电介质层。 在电介质层的下表面嵌入较低的电路图案。 较低电路图案包括具有第一厚度的迹线和具有大于第一厚度的第二厚度的延伸着陆焊盘。 通过孔的盲孔通过嵌入电介质层的上表面的上电路图案形成，穿过电介质层和扩展的着陆焊盘。 盲孔通孔的长度由于与第一厚度的迹线相比扩大的着陆焊盘的第二厚度增加而最小化。 因此，电介质层上表面处的盲孔通孔的宽度最小化。

公开(公告)号：US20140134800A1

公开(公告)日：2014-05-15

申请号：US13678026

申请日：2012-11-15

申请人： Michael G. Kelly ,  David Jon Hiner ,  Ronald Patrick Huemoeller

发明人： Michael G. Kelly ,  David Jon Hiner ,  Ronald Patrick Huemoeller

IPC分类号： H01L21/78 ,  H01L21/762

CPC分类号： H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L22/14 ,  H01L22/20 ,  H01L23/04 ,  H01L23/147 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81908 ,  H01L2224/81986 ,  H01L2224/83192 ,  H01L2224/83908 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/00

摘要： Methods for temporary wafer molding for chip-on-wafer assembly may include bonding one or more semiconductor die to an interposer wafer, applying a temporary mold material to encapsulate the bonded die, and backside processing the interposer, which may be singulated to generate assemblies comprising the bonded die, the interposer die, which may be bonded to packaging substrates. The temporary mold material may be removed and the bonded die may be tested. Additional die may be bonded to the assemblies based on the electrical testing. The interposer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The backside processing may comprise thinning the interposer wafer to expose through-silicon-vias (TSVs) and placing metal contacts on the exposed TSVs. The die may be bonded to the interposer utilizing a mass reflow or thermal compression process.

摘要翻译： 用于片上晶片组装的临时晶片成型的方法可以包括将一个或多个半导体管芯接合到插入器晶片，施加临时模制材料以封装接合的管芯，以及背面处理插入件，其可以被单个化以产生组件， 可以粘合到封装衬底上的粘合模，插入模。 可以移除临时模具材料并且可以测试粘合的模具。 基于电气测试，附加模具可以结合到组件。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器。 背面处理可以包括使内插器晶片变薄以暴露穿过硅通孔（TSV）并将金属触点放置在暴露的TSV上。 可以使用质量回流或热压缩工艺将管芯结合到插入件。

公开(公告)号：US20140134796A1

公开(公告)日：2014-05-15

申请号：US13678046

申请日：2012-11-15

申请人： Michael G. Kelly ,  Ronald Patrick Huemoeller ,  Won Chul Do ,  David Jon Hiner

发明人： Michael G. Kelly ,  Ronald Patrick Huemoeller ,  Won Chul Do ,  David Jon Hiner

IPC分类号： H01L21/50

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/50 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L27/108 ,  H01L2221/68381 ,  H01L2224/13147 ,  H01L2224/29011 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/75704 ,  H01L2224/75744 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.

摘要翻译： 公开了具有管芯到插入件晶片第一接合的半导体器件封装的方法和系统，并且可以包括将包括电子器件的多个半导体管芯结合到插入器晶片，以及在管芯和插入器晶片之间施加底部填充材料。 可以应用模具材料来封装模具。 内插器晶片可以被薄化以暴露通过硅通孔（TSV），并且可以将金属触点施加到暴露的TSV。 内插器晶片可以被单个化以产生包括半导体管芯和插入器管芯的组件。 可以使用粘合剂膜将管芯放置在插入件晶片上。 可以使用激光切割工艺，反应离子蚀刻，锯切技术和等离子体蚀刻工艺中的一种或多种来切割插入器晶片。 可以使用质量回流或热压缩工艺将管芯结合到插入件晶片。

公开(公告)号：US08501543B1

公开(公告)日：2013-08-06

申请号：US13472961

申请日：2012-05-16

申请人： Christopher John Berry ,  Ronald Patrick Huemoeller ,  David Jon Hiner

发明人： Christopher John Berry ,  Ronald Patrick Huemoeller ,  David Jon Hiner

IPC分类号： H01L21/00

CPC分类号： H01L24/96 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/82

摘要： A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby avoiding the use of photoimagable materials and photo-etching processes.

摘要翻译： 一种方法和结构提供了直接写入晶片级芯片级封装（DWWLCSP），其利用永久层/涂层和直接写入技术对这些层/涂层进行图案化，从而避免使用光可塑材料和光蚀刻工艺。