公开(公告)号：US20110079901A1

公开(公告)日：2011-04-07

申请号：US12968794

申请日：2010-12-15

申请人： Glenn A. Rinne ,  Kevin Engel ,  Julia Roe ,  Chirstopher John Berry

发明人： Glenn A. Rinne ,  Kevin Engel ,  Julia Roe ,  Chirstopher John Berry

IPC分类号： H01L23/498

CPC分类号： H01L23/3114 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05099

摘要： A method of processing a wafer including a plurality of integrated circuit devices on a front side of the wafer, may include thinning the wafer from a back side opposite the front side. After thinning the wafer, a back side layer may be provided on the back side of the thinned wafer opposite the front side, and the back side layer may be configured to counter stress on the front side of the wafer including the plurality of integrated circuit devices thereon. After providing the back side layer, the plurality of integrated circuit devices may be separated. Related structures are also discussed.

摘要翻译： 在晶片前侧处理包括多个集成电路器件的晶片的方法可以包括从与前侧相反的背面使晶片变薄。 在使晶片变薄之后，可以在与正面相反的薄化晶片的背面上设置背面层，并且背面层可以被配置为抵抗包括多个集成电路器件的晶片的前侧上的应力 上。 在提供背面层之后，可以分离多个集成电路装置。 还讨论了相关结构。

公开(公告)号：US07834454B2

公开(公告)日：2010-11-16

申请号：US12194999

申请日：2008-08-20

申请人： Glenn A. Rinne ,  J. Daniel Mis

发明人： Glenn A. Rinne ,  J. Daniel Mis

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/062 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2924/00014 ,  H01L2924/013

摘要： Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask.

摘要翻译： 形成电子结构可以包括在基底上形成种子层，并在种子层上形成掩模。 掩模可以包括其中露出种子层的一部分的孔，并且阻挡层可以形成在种子层的暴露部分上。 可以在阻挡层上形成凸起，并且可以去除掩模。 此外，可以使用阻挡层作为蚀刻掩模来选择性地去除种子层的部分。

公开(公告)号：US07674701B2

公开(公告)日：2010-03-09

申请号：US11671018

申请日：2007-02-05

申请人： Glenn A. Rinne

发明人： Glenn A. Rinne

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L21/0272 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11474 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014

摘要： Methods of forming interconnections for an electronic device including a substrate may be provided. For example, first and second patterned layers may be formed on the substrate wherein an opening in the first and second patterned layers exposes portions of the substrate, wherein the first and second patterned layers have different compositions, and wherein the first patterned layer is between the second patterned layer and the substrate. A metal layer may be formed on the second patterned layer and on portions of the substrate exposed through the opening in the first and second patterned layers. The second patterned layer and portions of the metal layer thereon may be removed while maintaining portions of the metal layer on the portions of the substrate exposed through the opening. After removing the second mask layer, solder may be provided on the metal layer.

摘要翻译： 可以提供形成用于包括衬底的电子设备的互连的方法。 例如，第一和第二图案化层可以形成在衬底上，其中第一和第二图案化层中的开口露出衬底的部分，其中第一和第二图案化层具有不同的组成，并且其中第一图案化层位于 第二图案层和衬底。 金属层可以形成在第二图案化层上，并且在衬底的部分通过第一和第二图案化层中的开口暴露。 第二图案化层及其上的金属层的部分可被去除，同时保持金属层的部分通过开口露出的部分。 在去除第二掩模层之后，可以在金属层上提供焊料。

公开(公告)号：US07297631B2

公开(公告)日：2007-11-20

申请号：US11226569

申请日：2005-09-14

申请人： Krishna K. Nair ,  Glenn A. Rinne ,  William E. Batchelor

发明人： Krishna K. Nair ,  Glenn A. Rinne ,  William E. Batchelor

IPC分类号： H01L21/44

CPC分类号： H01L23/528 ,  H01L21/2885 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/13099 ,  H01L2924/00

摘要： Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.

摘要翻译： 形成电子结构的方法可以包括在电子衬底上形成种子层，以及在种子层的部分上形成导电分流层，其中种子层的部分没有导电分流层。 导电阻挡层可以形成在与种子层相对的导电分流层上，其中导电分流层包括第一材料，并且其中阻挡层包括不同于第一材料的第二材料。 此外，可以在与导电分流层相对的阻挡层上形成焊料层，其中焊料层包括不同于第一和第二材料的第三材料。 还讨论了相关结构。

公开(公告)号：US20070182004A1

公开(公告)日：2007-08-09

申请号：US11671026

申请日：2007-02-05

申请人： Glenn A. Rinne

发明人： Glenn A. Rinne

IPC分类号： H01L23/48

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/17 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/013

摘要： An electronic device may include a substrate with an input/output pad thereon, and a compliant dielectric layer on a first portion of the substrate such that a second portion of the substrate is free of the compliant dielectric layer. A conductive redistribution line may extend from the input/output pad to the compliant dielectric layer so that the compliant dielectric layer is between a bump pad portion of the conductive redistribution line and the substrate. A first solder bump may be on the bump pad portion of the conductive redistribution line so that the compliant dielectric layer is between the first solder bump and the substrate. A second solder bump may be on the second portion of the substrate that is free of the compliant dielectric layer. Related methods are also discussed.

摘要翻译： 电子器件可以包括其上具有输入/输出焊盘的衬底，以及在衬底的第一部分上的柔性介电层，使得衬底的第二部分不含柔性介电层。 导电再分布线可以从输入/输出焊盘延伸到柔性介电层，使得柔性介电层位于导电再分配线的凸块焊盘部分和衬底之间。 第一焊料凸块可以在导电再分配线的凸块焊盘部分上，使得柔性介电层位于第一焊料凸块和衬底之间。 第二焊料凸块可以在基板的第二部分上，该第二部分不含柔性介电层。 还讨论了相关方法。

公开(公告)号：US07156284B2

公开(公告)日：2007-01-02

申请号：US10790967

申请日：2004-03-02

申请人： Glenn A. Rinne ,  Krishna K. Nair

发明人： Glenn A. Rinne ,  Krishna K. Nair

IPC分类号： B23K31/02

CPC分类号： G02B6/3628 ,  B23K1/0004 ,  G02B6/3636 ,  G02B6/3692

摘要： Methods of bonding two components may include positioning the components relative to one another to obtain a desired orientation. Once the desired orientation is obtained, the components can be bonded in the desired orientation with metal wherein a temperature of both components is maintained below a melting temperature of the metal while bonding. Related structures are also discussed.

摘要翻译： 粘合两个部件的方法可以包括相对于彼此定位组件以获得期望的取向。 一旦获得了所需的取向，就可以将金属成分按期望的方向与金属结合，其中两种成分的温度在粘合时保持在金属的熔融温度以下。 还讨论了相关结构。

公开(公告)号：US06666368B2

公开(公告)日：2003-12-23

申请号：US10016270

申请日：2001-11-02

申请人： Glenn A. Rinne

发明人： Glenn A. Rinne

IPC分类号： B23K3102

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/0212 ,  H05K3/3436 ,  H05K2201/10484 ,  H05K2203/0278 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

摘要： A second substrate is positioned relative to a first substrate having phase-changeable bumps, such as solder bumps, between them, wherein the second substrate has a first face adjacent the first substrate, a second face remote from the first substrate, and at least one edge wall between the first and second faces. The phase-changeable bumps are liquefied to establish an equilibrium position of the first and second substrates relative to one another. At least a portion of the second face is pushed away from the equilibrium position towards the first substrate, to a new position, without applying external force to the first face other than spring forces of the phase-changeable bumps that are liquefied, and without applying external force to any edge wall. Thus, only spring forces of the phase-changeable bumps that are liquefied oppose the pushing. The phase-changeable bumps that are liquefied then are solidified, to maintain the new position.

公开(公告)号：US06418033B1

公开(公告)日：2002-07-09

申请号：US09714311

申请日：2000-11-16

申请人： Glenn A. Rinne

发明人： Glenn A. Rinne

IPC分类号： H05K111

CPC分类号： H05K1/11 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2224/0401

摘要： Microelectronic packages include a first microelectronic substrate, a second microelectronic substrate that is oriented at an acute angle relative to the first microelectronic substrate, and first solder bumps between the first and second microelectronic substrates, adjacent an edge of the second microelectronic substrate, that connect the second microelectronic substrate to the first microelectronic substrate and that are confined to within the edge of the second microelectronic substrate. The edge of the second microelectronic substrate is adjacent the vertex of the acute angle. A third microelectronic substrate also may be provided on the first microelectronic substrate that laterally overlaps the second microelectronic substrate. Second solder bumps connect the third microelectronic substrate to the first microelectronic substrate. The second and third microelectronic substrates may be oriented parallel to one another at the acute angle relative to the first microelectronic substrate. Alternatively, second solder bumps are adjacent a first edge of the third microelectronic substrate and opposite a second edge of the third microelectronic substrate, wherein the second edge of the third microelectronic substrate is adjacent the vertex and wherein the first edge of the third microelectronic substrate is opposite the vertex.

摘要翻译： 微电子封装包括第一微电子衬底，相对于第一微电子衬底定向成锐角的第二微电子衬底以及邻近第二微电子衬底边缘的第一和第二微电子衬底之间的第一焊料凸点， 第二微电子衬底到第一微电子衬底并被限制在第二微电子衬底的边缘内。 第二微电子衬底的边缘与锐角的顶点相邻。 也可以在第一微电子衬底上提供第三微电子衬底，其横向地与第二微电子衬底重叠。 第二焊料凸块将第三微电子衬底连接到第一微电子衬底。 第二和第三微电子衬底可以相对于第一微电子衬底以锐角相互平行取向。 或者，第二焊料凸块与第三微电子衬底的第一边缘相邻并且与第三微电子衬底的第二边缘相对，其中第三微电子衬底的第二边缘与顶点相邻，并且其中第三微电子衬底的第一边缘是 顶点对面

公开(公告)号：US6117299A

公开(公告)日：2000-09-12

申请号：US854075

申请日：1997-05-09

申请人： Glenn A. Rinne ,  Christine Lizzul

发明人： Glenn A. Rinne ,  Christine Lizzul

IPC分类号： C25D7/12 ,  H01L21/60 ,  H01L23/12 ,  C25D5/02

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L23/5286 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107

摘要： Methods of electroplating solder bumps of uniform height on integrated circuit substrates include the steps of drawing plating current through an integrated circuit wafer by electrically shorting an integrated circuit's ground, power and signal pads together using an ultra-thin plating base layer (e.g.,

摘要翻译： 在集成电路基板上电镀均匀高度的焊料凸块的方法包括以下步骤：通过使用超薄电镀基底层将集成电路的接地，功率和信号焊盘电连接在一起，将电镀电流拉过集成电路晶片（例如，<0.075 μm厚），然后使用背面晶片接触件沿着延伸穿过地面和信号焊盘并进入衬底的平行路径绘制电镀电流。 接地焊盘优选地在衬底接触区域（例如，N +或P +扩散区域）处电耦合到衬底，并且信号焊盘优选地通过有源半导体器件（例如，FET，BJT等）电耦合到衬底。 ），信号垫被附着到其上。 优选通过集成电路的有源半导体器件和衬底接触区域平行地绘制电镀电流。 即使电镀底层具有小于约0.075μm的优选厚度，通过衬底接触区域和有源半导体器件的电镀电流的组合贡献足以将电镀基底层和下面的焊盘保持在均匀的电位。 这些均匀且典型的非零电位导致电镀速率通过限制通过电镀基层的横向电流流过晶片高度均匀。 电镀焊料凸块的均匀性也可以通过使用高密度控制崩溃芯片连接（C4）（“倒装芯片”）技术并通过在每个“倒装芯片”上散布接地和信号焊盘，从而增强每个信号焊盘 至少有一个接地垫作为最近的邻居。

公开(公告)号：US5381946A

公开(公告)日：1995-01-17

申请号：US127785

申请日：1993-09-27

申请人： Nicholas G. Koopman ,  Glenn A. Rinne ,  Iwona Turlik ,  Edward K. Yung

发明人： Nicholas G. Koopman ,  Glenn A. Rinne ,  Iwona Turlik ,  Edward K. Yung

IPC分类号： G01R31/26 ,  G01R31/28 ,  H01L21/326 ,  H01L21/66 ,  H01L23/58 ,  H01L21/60

CPC分类号： G01R31/2863 ,  H01L22/32 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/01014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15174 ,  H01L2924/15192 ,  Y10T29/49144

摘要： An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips. Solder bumps with different characteristics may be formed by varying the current-time product to each individual pad of the temporary substrate during a plating operation.

摘要翻译： 可以使用具有对应于芯片上的输入/输出焊盘的位置的衬底焊盘的临时衬底来测试其上具有焊料凸块的集成电路芯片，并且在临时衬底焊盘上具有牺牲导体层。 焊料凸点放置在相应的牺牲金属层附近，并被加热以在芯片和临时衬底之间形成电气和机械连接。 然后在临时衬底上测试和/或烧入芯片。 在测试/老化之后，通过加热将牺牲金属层溶解到焊料凸块中。 包括其中具有溶解的牺牲金属层的焊料凸块的集成电路芯片可以容易地从临时衬底移除。 也可以在临时衬底上形成焊料凸块并将其转移到未凸起的芯片。 可以通过在电镀操作期间通过改变临时衬底的每个单独衬垫的电流时间积来形成具有不同特性的焊料凸块。