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    Technologies for efficiently compressing data with multiple hash tables
    31.
    发明授权
    Technologies for efficiently compressing data with multiple hash tables 有权

    公开(公告)号：US10116327B2

    公开(公告)日：2018-10-30

    申请号：US15638842

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Daniel F. Cutter ,  Vinodh Gopal ,  James D. Guilford

    IPC: H03M7/30 ,  G06F17/30

    Abstract: Technologies for compressing data with multiple hash tables include a compute device. The compute device is to produce, for each of multiple string prefixes of different string prefix sizes, an associated hash. Each string prefix defines a set of consecutive symbols in a string that starts at a present position in an input stream of symbols. The compute device is also to write, to a different hash table for each string prefix size, a pointer to the present position in association with the associated hash. Each hash is usable as an index into the associated hash table to provide the present position of the string.

    LZ77 compression of data with data runs
    33.
    发明授权
    LZ77 compression of data with data runs 有权

    公开(公告)号：US10097201B1

    公开(公告)日：2018-10-09

    申请号：US15828137

    申请日：2017-11-30

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  Daniel F. Cutter

    IPC: H03M7/40 ,  H03M7/30

    Abstract: Methods and apparatus are described by for compressing data using LZ77 compression. Embodiments determine an initial run from input data. The initial run includes repeating data at a first location and has a first length. A hash chain is updated with a proper set of hashes from prefixes from the initial run. A first search engine determines a second run that includes the repeating data at a second location. The second run has a second length less than the first length. A first matching location is determined within the input data having the repeating data using the hash chain and the second run. The first matching location is the first location. The first matching location, the second location, and the second length are written to an output buffer. The output buffer includes a compressed version of the input data.

    Heterogeneous compression architecture for optimized compression ratio
    36.
    发明授权
    Heterogeneous compression architecture for optimized compression ratio 有权

    公开(公告)号：US09871535B2

    公开(公告)日：2018-01-16

    申请号：US15393599

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/34 ,  H03M7/40 ,  H03M7/30

    CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/3086

    Abstract: A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.

    Techniques for parallel data compression
    37.
    发明授权
    Techniques for parallel data compression 有权

    公开(公告)号：US09853660B1

    公开(公告)日：2017-12-26

    申请号：US15468061

    申请日：2017-03-23

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal ,  Kirk S. Yap ,  Daniel F. Cutter ,  James D. Guilford ,  Wajdi K. Feghali

    IPC: H03M7/00 ,  H03M7/34 ,  H03M7/30 ,  H03M7/40

    CPC classification number: H03M7/3086 ,  H03M7/40 ,  H03M7/6023

    Abstract: Techniques and apparatus for parallel data compression are described. An apparatus to provide parallel data compression may include at least one memory and logic for a compression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to provide at least one data input sequence to a plurality of compression components, determine compression information for the plurality of compression components, and perform a compression process on the at least one data input sequence via the plurality of compression components to generate at least one data output sequence, the plurality of compression components to perform the compression process in parallel based on the compression information.

    Supporting data compression using match scoring
    39.
    发明授权
    Supporting data compression using match scoring 有权
    使用匹配评分支持数据压缩

    公开(公告)号：US09594695B1

    公开(公告)日：2017-03-14

    申请号：US15229478

    申请日：2016-08-05

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/34 ,  G06F12/10 ,  G06F9/45

    CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0653 ,  G06F3/0673 ,  G06F8/52 ,  G06F12/1018 ,  G06F12/1027 ,  G06F2212/401 ,  G06F2212/68 ,  H03M7/3086 ,  H03M7/40

    Abstract: A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.

    Abstract translation: 提供一种处理系统，其包括用于存储输入比特流的存储器和可操作地耦合到存储器的处理逻辑，以便基于以下步骤产生第一分数：第一组匹配数据，其与第一比特子序列和 输入比特流内的候选比特子序列，以及候选比特子序列与第一组匹配数据的第一距离。 基于与第二比特子序列和候选比特子序列之间的匹配相关的第二组匹配数据以及候选比特子序列与第二组匹配数据的第二距离来生成第二分数。 识别用于替换输出比特流中的第一或第二比特子序列的代码。 选择要替换的比特子序列之一是基于得分的比较。

    Partitioned data compression using accelerator
    40.
    发明授权
    Partitioned data compression using accelerator 有权
    使用加速器分区数据压缩

    公开(公告)号：US09419647B2

    公开(公告)日：2016-08-16

    申请号：US14571658

    申请日：2014-12-16

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/40 ,  H03M7/30

    CPC classification number: H03M7/40 ,  H03M7/3086 ,  H03M7/6011

    Abstract: In an embodiment, a processor includes a compression accelerator coupled to a plurality of hardware processing cores. The compression accelerator is to: receive input data to be compressed; select a particular intermediate format of a plurality of intermediate formats based on a type of compression software to be executed by at least one of the plurality of hardware processing cores; perform a duplicate string elimination operation on the input data to generate a partially compressed output in the particular intermediate format; and provide the partially compressed output in the particular intermediate format to the compression software, wherein the compression software is to perform an encoding operation on the partially compressed output to generate a final compressed output. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括耦合到多个硬件处理核心的压缩加速器。 压缩加速器是：接收要压缩的输入数据; 基于由所述多个硬件处理核心中的至少一个执行的压缩软件的类型，选择多个中间格式的特定中间格式; 对输入数据执行重复字符串消除操作，以产生特定中间格式的部分压缩输出; 并将特定中间格式的部分压缩的输出提供给压缩软件，其中压缩软件将对部分压缩的输出执行编码操作以产生最终的压缩输出。 描述和要求保护其他实施例。

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