公开(公告)号：US20120061825A1

公开(公告)日：2012-03-15

申请号：US12906501

申请日：2010-10-18

申请人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/82001 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/18162

摘要： A chip scale package and a method of fabricating the chip scale package. The chip scale package includes a encapsulant having a first surface and a second surface opposing the first surface; a conductive pillar formed in the encapsulant and exposed from the first surface and the second surface; a chip embedded in the encapsulant while exposed from the first surface; a dielectric layer formed on the first surface, the conductive pillar and the chip; a circuit layer formed on the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer electrically connecting the circuit layer, electrode pads and the conductive pillar; and a solder mask layer formed on the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure.

摘要翻译： 一种芯片级封装和一种制造芯片级封装的方法。 芯片级封装包括具有第一表面和与第一表面相对的第二表面的密封剂; 形成在所述密封剂中并从所述第一表面和所述第二表面露出的导电柱; 在从第一表面暴露的同时嵌入密封剂中的芯片; 形成在所述第一表面上的电介质层，所述导电柱和所述芯片; 形成在电介质层上的电路层; 形成在电连接电路层，电极焊盘和导电柱的电介质层中的多个导电盲孔; 以及形成在电介质层和电路层上的焊料掩模层，从而根据需要使用导电柱来与其他电子器件外部连接以形成堆叠结构。

公开(公告)号：US20120032347A1

公开(公告)日：2012-02-09

申请号：US12971797

申请日：2010-12-17

申请人： Chiang-Cheng Chang ,  Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chiang-Cheng Chang ,  Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L25/07 ,  H01L23/48 ,  H01L21/98

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16221 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4644 ,  H01L2924/00014 ,  H01L2224/19 ,  H01L2224/11

摘要： A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product.

摘要翻译： 芯片级封装的制造方法包括提供电子元件，每个电子元件具有带有电极焊盘的活动表面和相对的无效表面，以及设置有软层的硬板; 通过其无效表面将电子部件粘附到软层; 按压电子部件，使得软层在暴露其活性表面的同时封装电子部件; 在电子部件和软质层的有源面上形成介电层; 并且在电介质层上形成第一布线层并与电极焊盘电连接，从而解决了直接将芯片粘附在粘合膜上的常规问题，例如膜软化，密封剂溢出，翘曲，芯片偏离和污染 导致在随后的RDL工艺中形成的电极焊盘和布线层之间的电连接不良甚至废物。

公开(公告)号：US20110156180A1

公开(公告)日：2011-06-30

申请号：US12769041

申请日：2010-04-28

申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

IPC分类号： H01L29/84 ,  H01L21/02 ,  H01L23/52

CPC分类号： H01L21/02 ,  B81B7/007 ,  B81B2207/07 ,  H01L23/52 ,  H01L29/84 ,  H01L2224/02166 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

摘要翻译： 提出具有微机电（MEMS）元件的封装结构，其包括具有多个电连接焊盘和形成在其上的MEMS元件的芯片; 设置在所述芯片上用于覆盖所述MEMS元件的盖; 设置在每个电连接焊盘上的螺柱凸块; 形成在芯片上的密封剂，其中一部分柱状凸块从密封剂暴露出来; 以及金属导电层，形成在密封剂上并连接到凸块上。 本发明的特征在于直接完成晶片上的封装工艺，以便在更短的时间内制造更薄和更便宜的封装结构。 本发明还提供如上所述的用于制造封装结构的方法。

公开(公告)号：US07934313B1

公开(公告)日：2011-05-03

申请号：US12759237

申请日：2010-04-13

申请人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H05K3/30

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A fabrication method of a package structure includes: preparing a metal plate having first and second surfaces and defined with an active region; forming a wiring layer with conductive traces and first electrical contact pads on the first surface; forming third electrical contact pads corresponding to the first electrical contact pads on the second surface; forming a first encapsulant on the first surface; forming on the second surface an open area to penetrate the metal plate, wherein the metal plate form conductive posts between the first and third electrical contact pads; mounting in the open area a chip electrically connected to the wiring layer; forming a second encapsulant in the open area, the wiring layer and the third electrical contact pads; forming first and second openings in the first and second encapsulants to expose the third electrical contact pads, respectively; and cutting the metal plate to remove the metal layer.

摘要翻译： 包装结构的制造方法包括：制备具有第一表面和第二表面并且限定有活性区域的金属板; 在所述第一表面上形成具有导电迹线和第一电接触焊盘的布线层; 形成对应于第二表面上的第一电接触焊盘的第三电接触焊盘; 在所述第一表面上形成第一密封剂; 在所述第二表面上形成穿透所述金属板的开放区域，其中所述金属板在所述第一和第三电接触焊盘之间形成导电柱; 在所述开放区域中安装与所述布线层电连接的芯片; 在所述开放区域中形成第二密封剂，所述布线层和所述第三电接触焊盘; 在第一和第二密封剂中形成第一和第二开口以分别露出第三电接触垫; 并切割金属板以去除金属层。

公开(公告)号：US20080296716A1

公开(公告)日：2008-12-04

申请号：US12151570

申请日：2008-05-07

申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

IPC分类号： H01L21/50 ,  H01L23/00

CPC分类号： H01L21/56 ,  H01L23/3114 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A sensor semiconductor device and a manufacturing method thereof are disclosed. The method includes: providing a light-permeable carrier board with a plurality of metallic circuits; electrically connecting the metallic circuits to a plurality of sensor chips through conductive bumps formed on the bond pads of the sensor chips, wherein the sensor chips have been previously subjected to thinning and chip probing; filling a first dielectric layer between the sensor chips to cover the metallic circuits and peripheries of the sensor chips; forming a second dielectric layer on the sensor chips and the first dielectric layer; forming grooves between the sensor chips for exposing the metallic circuits such that a plurality of conductive traces electrically connected to the metallic circuits can be formed on the second dielectric layer; and singulating the sensor chips to form a plurality of sensor semiconductor devices. The present invention overcomes the drawbacks of breakage of trace connection due to a sharp angle formed at joints, poor electrical connection and chip damage due to an alignment error in cutting from the back of the wafer, as well as an increased cost due to multiple sputtering processes for forming traces.

摘要翻译： 公开了一种传感器半导体器件及其制造方法。 该方法包括：提供具有多个金属电路的透光性载板; 通过形成在传感器芯片的接合焊盘上的导电凸块将金属电路电连接到多个传感器芯片，其中传感器芯片已经预先经受了薄化和芯片探测; 在传感器芯片之间填充第一电介质层以覆盖金属电路和传感器芯片的周边; 在所述传感器芯片和所述第一介电层上形成第二电介质层; 在所述传感器芯片之间形成用于暴露所述金属电路的槽，使得可以在所述第二介电层上形成电连接到所述金属电路的多个导电迹线; 并且分离传感器芯片以形成多个传感器半导体器件。 本发明克服了由于在接头处形成的尖角导致的迹线连接断裂的缺点，由于从晶片背面的切割中的对准误差导致的不良电连接和芯片损坏以及由于多次溅射而导致的成本增加 形成痕迹的过程。

公开(公告)号：US20080230913A1

公开(公告)日：2008-09-25

申请号：US12077223

申请日：2008-03-18

申请人： Chien-Ping Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Chun-Chi Ke

发明人： Chien-Ping Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Chun-Chi Ke

IPC分类号： H01L23/488 ,  H01L21/304

CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/05001 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provides a stackable semiconductor device and a fabrication method thereof, including providing a wafer having a plurality of dies mounted thereon, both the die and the wafer having an active surface and a non-active surface opposing one another respectively, wherein each die has a plurality of solder pads formed on the active surface thereof and a groove formed between adjacent solder pads to form a first metal layer therein that is electrically connected to the solder pads; subsequently thinning the non-active surface of the wafer to where the grooves are located to expose the first metal layer therefrom, and forming a second metal layer on the non-active surface of the wafer for electrically connecting with the first metal layer; and separating the dies to form a plurality of stackable semiconductor devices. Thereby, the first and second metal layers formed on the active surface and the non-active surface of the semiconductor device can be stacked and connected to constitute a multi-die stack structure, thereby increasing integration without increasing the area of the stacked dies. Further, the problems known in the prior art of poor electrical connection, complicated manufacturing process and increased cost as a result of using wire bonding and TSV can be avoided.

摘要翻译： 本发明提供了一种可堆叠半导体器件及其制造方法，包括提供具有安装在其上的多个管芯的晶片，晶粒和晶片两者分别具有相互相对的有源表面和非有效表面，其中每个管芯具有 形成在其有效表面上的多个焊盘和形成在相邻焊盘之间的槽，以在其中形成电连接到焊盘的第一金属层; 随后使所述晶片的非活性表面变薄到所述凹槽所在的位置以暴露出所述第一金属层，以及在所述晶片的非活性表面上形成用于与所述第一金属层电连接的第二金属层; 以及分离所述管芯以形成多个可堆叠的半导体器件。 由此，形成在半导体器件的有源表面和非有源表面上的第一和第二金属层可以被堆叠和连接以构成多管芯堆叠结构，从而增加集成度而不增加堆叠管芯的面积。 此外，可以避免由于使用引线接合和TSV而导致的不良电连接，复杂的制造工艺和增加的成本的现有技术中已知的问题。

公开(公告)号：US20080211093A1

公开(公告)日：2008-09-04

申请号：US12005483

申请日：2007-12-26

申请人： Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L21/60 ,  H01L23/488

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers.

摘要翻译： 提出了具有导电凸块的半导体器件及其制造方法。 该制造方法包括以下步骤：在具有焊盘和形成在其上的钝化层的基板上形成第一金属层，并将其电连接到焊盘; 在第一金属层的暴露部分上施加第二覆盖层; 随后在第二覆盖层上形成第二金属层，并将其电连接到第一金属层的暴露部分; 施加第三覆盖层，以及形成用于暴露第二金属层的部分的开口以在其上形成具有金属支座和焊料材料的导电凸块。 覆盖层和金属层可以提供缓冲效果，用于有效地吸收施加在导电凸块上的热应力，以防止由UBM层引起的分层。

公开(公告)号：US08963298B2

公开(公告)日：2015-02-24

申请号：US12769053

申请日：2010-04-28

申请人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/552 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L21/561 ,  H01L21/78 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.

摘要翻译： EMI屏蔽封装结构包括具有第一表面和芯片安装区域的基板单元和与第一表面相对的第二表面，形成在第一表面上的金属柱，安装在芯片安装区域上并与之电连接的芯片， 在将所述金属柱的一部分从所述密封剂暴露出来的同时覆盖所述芯片和所述第一表面的密封剂以及封装所述密封剂并电连接到所述金属柱的屏蔽膜。 进一步提供通过两个切割工艺的上述结构的制造方法。 第一切割工艺通过切割密封剂形成凹槽。 在凹槽中形成屏蔽膜并与金属柱电连接之后，通过第二切割工艺形成完整的封装结构，从而在克服现有技术中遇到的屏蔽膜的不良接地的同时简化制造工艺。

公开(公告)号：US08653661B2

公开(公告)日：2014-02-18

申请号：US13170424

申请日：2011-06-28

申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Shih-Kuang Chiu

发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Shih-Kuang Chiu

IPC分类号： H01L21/56

CPC分类号： B81C1/00301 ,  B81B2207/096 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A package structure having an MEMS element is provided, which includes: a protection layer having openings formed therein; conductors formed in the openings, respectively; conductive pads formed on the protection layer and the conductors; a MEMS chip disposed on the conductive pads; and an encapsulant formed on the protection layer for encapsulating the MEMS chip. By disposing the MEMS chip directly on the protection layer to dispense with the need for a carrier, such as a wafer or a circuit board that would undesirably add to the thickness, the present invention reduces the overall thickness of the package to thereby achieve miniaturization.

摘要翻译： 提供了具有MEMS元件的封装结构，其包括：形成有开口的保护层; 导体分别形成在开口中; 形成在保护层和导体上的导电焊盘; 设置在导电焊盘上的MEMS芯片; 以及形成在用于封装MEMS芯片的保护层上的密封剂。 通过将MEMS芯片直接设置在保护层上，以免对不希望地增加厚度的载体（例如晶片或电路板）的需要，本发明减小了封装的整体厚度从而实现小型化。

公开(公告)号：US08421199B2

公开(公告)日：2013-04-16

申请号：US12770028

申请日：2010-04-29

申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.