公开(公告)号：US06806192B2

公开(公告)日：2004-10-19

申请号：US10350837

申请日：2003-01-24

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L2144

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。

公开(公告)号：US09691706B2

公开(公告)日：2017-06-27

申请号：US13452140

申请日：2012-04-20

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/544 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/742 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2223/54426 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/24991 ,  H01L2224/82005 ,  H01L2224/82106 ,  H01L2224/8213 ,  H01L2224/82132 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00

Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

公开(公告)号：US09662812B2

公开(公告)日：2017-05-30

申请号：US13485307

申请日：2012-05-31

Applicant: Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: B29C43/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/1531 ,  H01L2924/157 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature.

公开(公告)号：US09153506B2

公开(公告)日：2015-10-06

申请号：US13542896

申请日：2012-07-06

Applicant: Chien Rhone Wang ,  Kewei Zuo ,  Chen-Hua Yu ,  Jing-Cheng Lin ,  Yen-Hsin Liu

Inventor： Chien Rhone Wang ,  Kewei Zuo ,  Chen-Hua Yu ,  Jing-Cheng Lin ,  Yen-Hsin Liu

IPC: G06F19/00 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L22/20 ,  H01L21/76898 ,  H01L22/12

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.

Abstract translation: 本公开提供了用于形成具有一个或多个贯穿硅通孔（TSV）特征的IC结构的集成电路（IC）制造方法的一个实施例。 IC制作方法包括执行多个处理步骤; 从多个处理步骤收集物理计量数据; 基于所述物理测量数据从所述多个处理步骤收集虚拟测量数据; 基于物理测量数据和虚拟测量数据，为IC结构生成产量预测; 以及基于所述产量预测在较早的处理步骤中识别动作。

公开(公告)号：US09117682B2

公开(公告)日：2015-08-25

申请号：US13270850

申请日：2011-10-11

Applicant: Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L21/78 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Abstract translation: 公开了封装半导体器件的方法及其结构。 在一个实施例中，一种封装半导体器件的方法包括提供载体晶片，提供多个管芯，以及在载体晶片上形成管芯洞穴材料。 在模具洞穴材料中形成多个模具洞穴。 将多个模具中的至少一个放置在模具洞穴材料中的多个模具洞穴的每一个中。 形成多个封装，所述多个封装中的每个封装形成在所述多个管芯中的相应的至少一个管芯上。

公开(公告)号：US09006004B2

公开(公告)日：2015-04-14

申请号：US13429054

申请日：2012-03-23

Applicant: Jing-Cheng Lin ,  Szu Wei Lu

Inventor： Jing-Cheng Lin ,  Szu Wei Lu

IPC: H01L21/66 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/563 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/11 ,  H01L2224/11002 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

Abstract translation: 一种方法包括将第一包装部件接合在第二包装部件的第一表面上，并且从第二包装部件的第二表面探测第一包装部件和第二包装部件。 通过探测第二包装部件的第二表面上的连接器来进行探测步骤。 连接器连接到第一包装部件。 在探测步骤之后，在第二包装部件的第一表面上结合第三包装部件。

公开(公告)号：US08803316B2

公开(公告)日：2014-08-12

申请号：US13311692

申请日：2011-12-06

Applicant: Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

Inventor： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/11011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/73204 ,  H01L2924/01028 ,  H01L2924/0132 ,  H01L2924/067 ,  H01L2924/0705 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

Abstract translation: 一种器件包括具有正面和背面的衬底，从衬底的背面延伸到前侧的通孔，以及位于衬底的背面和通孔上方的导电焊盘。 导电垫具有基本平坦的顶表面。 导电凸块在基本上平坦的顶表面上方具有非平面的顶表面，并且与通孔对准。 导电凸块和导电垫由相同的材料形成。 在导电凸块和导电垫之间不形成界面。

公开(公告)号：US08779588B2

公开(公告)日：2014-07-15

申请号：US13427753

申请日：2012-03-22

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H01L23/48

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13564 ,  H01L2224/1412 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/381

Abstract: The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package.

Abstract translation: 用于形成描述的多芯片封装的机构使得具有不同凸块尺寸的芯片被封装到公共衬底。 具有较大凸块的芯片可以与衬底上的两个或更多个更小的凸块接合。 相反，芯片上的两个或更多个小凸块可以与基板上的大凸块粘合。 通过允许具有不同尺寸的凸块结合在一起，具有不同凸块尺寸的芯片可以封装在一起以形成多芯片封装。

公开(公告)号：US08772929B2

公开(公告)日：2014-07-08

申请号：US13297992

申请日：2011-11-16

Applicant: Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

Abstract translation: 晶片级封装包括结合在支撑晶片上的半导体管芯。 半导体管芯在其衬底上至少有一个台阶凹槽。 在半导体管芯和支撑晶片之间形成底部填充层。 此外，底部填充层的高度受到台阶凹槽的限制。 在晶片级封装的制造过程中，台阶凹槽有助于减小晶片级封装上的应力。

公开(公告)号：US08703542B2

公开(公告)日：2014-04-22

申请号：US13539229

申请日：2012-06-29

Applicant: Jing-Cheng Lin ,  Jui-Pin Hung

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung

IPC: H01L21/50

CPC classification number: H01L24/10 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/82001 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.

Abstract translation: 上述晶片级封装（WLP）的机理的实施例利用平坦化停止层来确定形成再分配线（RDL）之前除去过量模塑料的终点。 WLP的这种机制被用于实现扇出和多芯片封装。 这些机构还可用于制造包括具有不同类型的外部连接的芯片（或模具）的包装。 例如，具有预先形成的凸块的模具可以与模具封装而没有预先形成的凸块。