公开(公告)号：US08264084B2

公开(公告)日：2012-09-11

申请号：US11932845

申请日：2007-10-31

申请人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

发明人： François Hébert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

IPC分类号： H01L21/60 ,  H01L23/488

CPC分类号： H01L24/40 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/64 ,  H01L24/29 ,  H01L24/33 ,  H01L24/37 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/05624 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/37099

摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

摘要翻译： 提出了一种焊顶增强型半导体器件进行封装。 焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。 至少一个接触区域电连接到至少一个接触增强区域。 每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。 在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。 用于制造焊料顶部器件的方法包括：a）将顶部金属层的光刻图案化成接触区域和接触增强区域。 b）使用用于增加复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

公开(公告)号：US07781265B2

公开(公告)日：2010-08-24

申请号：US12384100

申请日：2009-03-30

申请人： Xiaotian Zhang ,  Kai Liu ,  Ming Sun

发明人： Xiaotian Zhang ,  Kai Liu ,  Ming Sun

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A dual flat non-leaded semiconductor package is disclosed. A method of making a dual flat non-leaded semiconductor package includes forming a leadframe having a die bonding area with an integral drain lead, a gate lead bonding area and a source lead bonding area, the gate lead bonding area and a source lead bonding area being of increased area; bonding a die to the die bonding area; coupling a die source bonding area to the source lead bonding area; coupling a die gate bonding area to the gate lead bonding area; and partially encapsulating the die, the drain lead, the gate lead and the source lead to form the dual flat non-leaded semiconductor package.

摘要翻译： 公开了一种双平面无铅半导体封装。 制造双平面非铅半导体封装的方法包括：形成具有集成漏极引线，栅极引线接合区域和源极引线接合区域的管芯接合区域的引线框架，栅极引线接合区域和源极引线接合区域 面积增加; 将管芯结合到管芯接合区域; 将管芯源极接合区域耦合到所述源极引线接合区域; 将栅极接合区域耦合到栅极引线接合区域; 并且部分地封装裸片，漏极引线，栅极引线和源极引线，以形成双平面非引线半导体封装。

公开(公告)号：US20090108456A1

公开(公告)日：2009-04-30

申请号：US11932845

申请日：2007-10-31

申请人： Francois Hebert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

发明人： Francois Hebert ,  Anup Bhalla ,  Kai Liu ,  Ming Sun

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/40 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/64 ,  H01L24/29 ,  H01L24/33 ,  H01L24/37 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/05624 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/37099

摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

摘要翻译： 提出了一种焊顶增强型半导体器件进行封装。 焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。 至少一个接触区域电连接到至少一个接触增强区域。 每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。 在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。 用于制造焊料顶部器件的方法包括：a）将顶部金属层的光刻图案化成接触区域和接触增强区域。 b）使用用于增加复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

公开(公告)号：US20080182387A1

公开(公告)日：2008-07-31

申请号：US11701561

申请日：2007-01-31

申请人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

发明人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/288 ,  H01L21/6836 ,  H01L24/02 ,  H01L24/11 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014

摘要： A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.

摘要翻译： 公开了一种在湿法处理中制造采用化学镀的半导体器件的方法，包括晶片背面保护。 该方法包括以下步骤：将晶片背面和框架与保护带层压，将保护涂层施加到晶片的周边部分以及相邻的保护带的暴露区域，保护涂层，保护带和晶片成形 保护的晶片组件，固化框架支撑的保护涂层，将保护的晶片组件从围绕保护涂层的保护带切割，湿处理受保护的晶片组件，用第二带层压受保护的晶片组件，切割晶片，以及拾取 从保护胶带上取下模具。

公开(公告)号：US09731242B2

公开(公告)日：2017-08-15

申请号：US15028478

申请日：2013-11-06

申请人： XiaoShan Zhou ,  Ming Sun ,  Ji Lei

发明人： XiaoShan Zhou ,  Ming Sun ,  Ji Lei

IPC分类号： B01D53/047 ,  B01D53/06

CPC分类号： B01D53/06 ,  B01D53/047 ,  B01D2253/108 ,  B01D2253/116 ,  B01D2259/40003

摘要： A pressure swing adsorption apparatus having: a housing with an arc-shaped inner surface, the housing being arranged with at least one gas inlet, at least one exhaust port and at least one gas outlet for discharging the separated gas; a rotor arranged in the housing, at least two contact ends being arranged on the rotor for maintaining a non-stop sliding contact with the inner surface of the housing, individual cavities, i.e., air cavities between the adjacent contact ends and formed between the external surface of the rotor and the inner surface of the housing, and each air cavity being separated by the contact ends; adsorption chambers set inside the rotor as parts of the rotor and rotated along with the rotor, molecular sieves being loaded in the interior of the adsorption chambers, and the adsorption chambers being provided with screen openings for connection with the air cavities.

公开(公告)号：US08670211B1

公开(公告)日：2014-03-11

申请号：US13164991

申请日：2011-06-21

申请人： Ming Sun ,  Jose A. Medina ,  Keith Y. Sasaki ,  Ming Jiang

发明人： Ming Sun ,  Jose A. Medina ,  Keith Y. Sasaki ,  Ming Jiang

IPC分类号： G11B5/127 ,  C25D3/00

CPC分类号： G11B5/3143 ,  C25D3/562 ,  C25D5/18 ,  C25D7/001 ,  G11B5/3163 ,  H01F41/26

摘要： A method and system plates CoFeX, where X is an insertion metal. The method and system include providing a plating solution including hydroxymethyl-p-tolylsulfone (HPT). The plating solution being configured to provide a CoFeX film having a high saturation magnetic flux density of greater than 2.3 Tesla and not more than 3 weight percent of X. The method and system also include plating the CoFeX film on a substrate in the plating solution. In some aspects, the plated CoFeX film may be used in structures such as main poles of a magnetic recording head.

摘要翻译： 一种方法和系统板CoFeX，其中X是插入金属。 该方法和系统包括提供包含羟甲基对甲苯砜（HPT）的电镀溶液。 电镀溶液被配置为提供具有大于2.3特斯拉的高饱和磁通密度和不大于X重量百分比的X的高的饱和磁通密度的CoFeX膜。该方法和系统还包括在电镀液中的基底上电镀CoFeX膜。 在一些方面，电镀CoFeX膜可以用于诸如磁记录头的主极的结构中。

公开(公告)号：US20130006982A1

公开(公告)日：2013-01-03

申请号：US13497857

申请日：2010-06-03

申请人： Ming Sun

发明人： Ming Sun

IPC分类号： G06F17/30

CPC分类号： G06F11/3476 ,  G06F11/3409 ,  G06F17/30339 ,  H04L41/0823 ,  H04L41/0853

摘要： A method and system for storing performance data are disclosed, and the method includes: during a process of adding a collection point, a system creating a data subtable in real time according to the number of added collection points and a predetermined maximum number of collection points of the data subtable; and storing the performance data of the collection point into the created data subtable, and storing the corresponding relationship between the collection point and the data subtable.

摘要翻译： 公开了一种存储性能数据的方法和系统，该方法包括：在添加收集点的过程中，根据添加的收集点的数量和预定的最大数量的收集点，实时地生成数据的系统 的数据子表; 并将所述收集点的演奏数据存储在所生成的数据中，并且存储所述收集点和所述数据之间的对应关系。

公开(公告)号：US08343801B2

公开(公告)日：2013-01-01

申请号：US13278240

申请日：2011-10-21

申请人： Ming Sun ,  Michael Xuefei Tang ,  Insik Jin ,  Venkatram Venkatasamy ,  Philip George Pitcher ,  Nurul Amin

发明人： Ming Sun ,  Michael Xuefei Tang ,  Insik Jin ,  Venkatram Venkatasamy ,  Philip George Pitcher ,  Nurul Amin

IPC分类号： H01L21/00 ,  H01L21/16

CPC分类号： H01L45/085 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146

摘要： Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.

摘要翻译： 可编程金属化存储单元包括在电化学活性电极和惰性电极之间的电化学活性电极和惰性电极以及离子导体固体电解质材料。 电绝缘氧化物层将离子导体固体电解质材料与电化学活性电极分离。

公开(公告)号：US08334165B2

公开(公告)日：2012-12-18

申请号：US12761899

申请日：2010-04-16

申请人： Haiwen Xi ,  Ming Sun ,  Dexin Wang ,  Shuiyuan Huang ,  Michael Tang ,  Song S. Xue

发明人： Haiwen Xi ,  Ming Sun ,  Dexin Wang ,  Shuiyuan Huang ,  Michael Tang ,  Song S. Xue

IPC分类号： H01L21/00

CPC分类号： H01L45/085 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/143 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1658 ,  H01L45/1675

摘要： Methods for making a programmable metallization memory cell are disclosed.

摘要翻译： 公开了制造可编程金属化存储单元的方法。

公开(公告)号：US08330264B2

公开(公告)日：2012-12-11

申请号：US13454342

申请日：2012-04-24

申请人： Ming Sun ,  Yueh Se Ho

发明人： Ming Sun ,  Yueh Se Ho

IPC分类号： H01L23/12

CPC分类号： H01L23/49816 ,  H01L23/3677 ,  H01L23/49844 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00

摘要： This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.