公开(公告)号：US20160064324A1

公开(公告)日：2016-03-03

申请号：US14469645

申请日：2014-08-27

申请人： Sergio A. Ajuria ,  Phuc M. Nyugen ,  Douglas M. Reber

发明人： Sergio A. Ajuria ,  Phuc M. Nyugen ,  Douglas M. Reber

IPC分类号： H01L23/522 ,  H01L21/283 ,  H01L49/02 ,  H01L21/78

CPC分类号： H01L28/60 ,  H01L23/3114 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/5223 ,  H01L24/02 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/24137 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

摘要翻译： 描述了具有嵌入式电容器的半导体封装和相应的制造方法。 具有嵌入式电容器的半导体封装包括半导体管芯，该半导体管芯具有延伸穿过半导体管芯的第一侧的至少一部分的第一金属层和形成在半导体管芯的第一侧上的封装结构。 嵌入式电容器的第一电导体形成在半导体管芯的第一金属层中。 封装结构包括在其中形成有嵌入式电容器的第二电导体的第二金属层。 嵌入式电容器的电介质位于半导体管芯或半导体封装的封装结构内，以使第一电导体与嵌入式电容器的第二电导体隔离。

公开(公告)号：US09041209B2

公开(公告)日：2015-05-26

申请号：US13299566

申请日：2011-11-18

申请人： Douglas M. Reber ,  Lawrence N. Herr

发明人： Douglas M. Reber ,  Lawrence N. Herr

IPC分类号： H01L23/498 ,  G06F17/50 ,  H01L21/768

CPC分类号： G06F17/5068 ,  H01L21/76814 ,  H01L21/76828

摘要： In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

摘要翻译： 在公开的实施例中，在具有多个通孔的半导体器件中平铺所选择的通孔的方法包括生成用于半导体器件的布局数据库; 在多个通孔周围创建区域; 测量每个区域的覆盖金属的密度; 选择低密度区域是具有小于阈值金属密度的金属密度的区域; 并且在低密度区域中的多个通孔上方的金属层上添加至少一个平铺特征，使得低密度区域的金属密度增加至至少与阈值金属密度相同。

公开(公告)号：US06972255B2

公开(公告)日：2005-12-06

申请号：US10628668

申请日：2003-07-28

申请人： Douglas M. Reber ,  Mark D. Hall ,  Kurt H. Junker ,  Kyle W. Patterson ,  Tab Allen Stephens ,  Edward K. Theiss ,  Srikanteswara Dakshiina-Murthy ,  Marilyn Irene Wright

发明人： Douglas M. Reber ,  Mark D. Hall ,  Kurt H. Junker ,  Kyle W. Patterson ,  Tab Allen Stephens ,  Edward K. Theiss ,  Srikanteswara Dakshiina-Murthy ,  Marilyn Irene Wright

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/44

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/31612 ,  H01L21/32139 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/902 ,  Y10S438/952

摘要： In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.

摘要翻译： 在制造半导体器件中，待蚀刻的导电材料上方的图案化叠层具有图案化的光致抗蚀剂层，其用于对四乙基原硅酸盐（TEOS）层进行图案化。 在比常规温度低的温度下沉积TEOS层。 低温TEOS层位于导电层上方的有机抗反射涂层（ARC）上。 低温TEOS层提供有机ARC和光致抗蚀剂之间的粘附，具有低缺陷性，作为硬掩模操作，并且用作与有机ARC组合有助于减少不期望的反射的相移层。

公开(公告)号：US09548266B2

公开(公告)日：2017-01-17

申请号：US14469645

申请日：2014-08-27

申请人： Sergio A. Ajuria ,  Phuc M. Nyugen ,  Douglas M. Reber

发明人： Sergio A. Ajuria ,  Phuc M. Nyugen ,  Douglas M. Reber

IPC分类号： H01L23/522 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01L23/3114 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/5223 ,  H01L24/02 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/24137 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

摘要翻译： 描述了具有嵌入式电容器的半导体封装和相应的制造方法。 具有嵌入式电容器的半导体封装包括半导体管芯，该半导体管芯具有延伸穿过半导体管芯的第一侧的至少一部分的第一金属层和形成在半导体管芯的第一侧上的封装结构。 嵌入式电容器的第一电导体形成在半导体管芯的第一金属层中。 封装结构包括在其中形成有嵌入式电容器的第二电导体的第二金属层。 嵌入式电容器的电介质位于半导体管芯或半导体封装的封装结构内，以使第一电导体与嵌入式电容器的第二电导体隔离。

公开(公告)号：US20150200146A1

公开(公告)日：2015-07-16

申请号：US14153417

申请日：2014-01-13

申请人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

发明人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L23/29 ,  H01L23/10 ,  H01L21/78

CPC分类号： H01L22/34 ,  H01L21/78 ,  H01L22/32 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.

摘要翻译： 公开了使用在划线中形成的一次性测试电路的半导体制造的实施例。 制造步骤可以包括在半导体管芯内形成器件电路并在划线内形成测试电路。 还形成一个或多个连接设备电路和测试电路块的电连接路线。 此外，每个管芯可以连接到单个测试电路块，或者多个管芯可以共享公共测试电路块。 测试后，电气连接路线被密封，并且当设备裸片被切割时，测试电路被丢弃。 对于某些实施例，器件裸片的边缘被保护金属层封装，并且某些其它实施例包括保护性密封件，连接路线经过该保护密封件从划线中的测试电路块进入骰子。

公开(公告)号：US08486839B2

公开(公告)日：2013-07-16

申请号：US13114100

申请日：2011-05-24

申请人： Douglas M. Reber ,  Lawrence N. Herr

发明人： Douglas M. Reber ,  Lawrence N. Herr

IPC分类号： H01L21/311

CPC分类号： H01L21/76816 ,  G06F17/5081

摘要： A method for tiling selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and adding tiling features on a metal layer above the selected isolated vias and within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.

摘要翻译： 提供了一种在半导体器件中平铺所选择的通孔的方法。 半导体器件包括多个通孔。 该方法包括：生成用于半导体器件的布局数据库; 识别多个通孔中的隔离通孔; 选择隔离通孔; 在每个所选择的隔离通孔周围限定区域; 以及在所选择的隔离通孔上方和区域内的金属层上添加平铺特征。 该方法通过允许湿气从通孔周围排出来提高半导体器件的可靠性。

公开(公告)号：US20120178189A1

公开(公告)日：2012-07-12

申请号：US12985906

申请日：2011-01-06

申请人： Douglas M. Reber

发明人： Douglas M. Reber

IPC分类号： H01L21/60 ,  H01L21/66

CPC分类号： H01L24/03 ,  H01L22/32 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/03442 ,  H01L2224/03505 ,  H01L2224/03552 ,  H01L2224/03554 ,  H01L2224/03901 ,  H01L2224/0392 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05013 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of making a semiconductor structure includes forming a bond pad, depositing by laser defined deposition a conductive pad, and attaching an electrical connector to the conductive pad. The bond pad is a portion of an integrated circuit. The bond pad includes an exposed portion. The bond pad functions as a contact to the integrated circuit. The conductive pad is deposited on the exposed portion and is confined within a bond pad region around the exposed portion of the bond pad

摘要翻译： 制造半导体结构的方法包括形成接合焊盘，通过激光定义沉积沉积导电焊盘，以及将电连接器附接到导电焊盘。 接合焊盘是集成电路的一部分。 接合焊盘包括暴露部分。 接合焊盘作为集成电路的触点。 导电焊盘沉积在暴露部分上，并被限制在接合焊盘暴露部分周围的接合焊盘区域内

公开(公告)号：US08039389B2

公开(公告)日：2011-10-18

申请号：US11676100

申请日：2007-02-16

申请人： Douglas M. Reber ,  Mark D. Hall ,  Kurt H. Junker ,  Kyle W. Patterson ,  Tab Allen Stephens ,  Edward K. Theiss ,  Srikanteswara Dakshiina-Murthy ,  Marilyn Irene Wright

发明人： Douglas M. Reber ,  Mark D. Hall ,  Kurt H. Junker ,  Kyle W. Patterson ,  Tab Allen Stephens ,  Edward K. Theiss ,  Srikanteswara Dakshiina-Murthy ,  Marilyn Irene Wright

IPC分类号： H01L21/4763

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/31612 ,  H01L21/32139 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/902 ,  Y10S438/952

摘要： In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.

摘要翻译： 在制造半导体器件中，待蚀刻的导电材料上方的图案化叠层具有图案化的光致抗蚀剂层，其用于对四乙基原硅酸盐（TEOS）层进行图案化。 在比常规温度低的温度下沉积TEOS层。 低温TEOS层位于导电层上方的有机抗反射涂层（ARC）上。 低温TEOS层提供有机ARC和光致抗蚀剂之间的粘附，具有低缺陷性，作为硬掩模操作，并且用作与有机ARC组合有助于减少不期望的反射的相移层。

公开(公告)号：US06713381B2

公开(公告)日：2004-03-30

申请号：US10051262

申请日：2002-01-18

申请人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

发明人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/54473 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2924/013 ,  H01L2924/0496 ,  H01L2924/0539 ,  H01L2924/0538 ,  H01L2924/0537

摘要： An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

摘要翻译： 互连覆盖半导体器件衬底（10）。 在一个实施例中，导电阻挡层覆盖在互连的一部分上，钝化层（92）覆盖在导电阻挡层上，钝化层（92）具有暴露导电阻挡层（82）的部分的开口。 在替代实施例中，钝化层（22）覆盖互连，钝化层（22）具有暴露互连的开口（24），并且导电阻挡层（32）覆盖开口（24）内的互连。

公开(公告)号：US09601354B2

公开(公告)日：2017-03-21

申请号：US14470383

申请日：2014-08-27

申请人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

发明人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

IPC分类号： H01L21/66 ,  H01L21/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/58

CPC分类号： H01L21/4846 ,  H01L22/34 ,  H01L23/522 ,  H01L23/562 ,  H01L23/585 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/039 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81203 ,  H01L2224/85048 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/8581 ,  H01L2224/92 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.