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公开(公告)号：US20170338186A1
公开(公告)日：2017-11-23
申请号：US15669273
申请日：2017-08-04
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Fu-Tang Huang , Chun-Chi Ke
IPC: H01L23/552 , H01L23/31 , H01L25/065 , H01L21/56 , H01L23/00 , H01L25/00
CPC classification number: H01L23/552 , H01L21/56 , H01L23/3121 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/91 , H01L24/92 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/02379 , H01L2224/02381 , H01L2224/04026 , H01L2224/04042 , H01L2224/05548 , H01L2224/05554 , H01L2224/05567 , H01L2224/06133 , H01L2224/06135 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/48132 , H01L2224/48137 , H01L2224/48227 , H01L2224/48235 , H01L2224/49052 , H01L2224/49107 , H01L2224/49175 , H01L2224/73215 , H01L2224/73257 , H01L2224/73265 , H01L2224/92165 , H01L2224/92247 , H01L2225/0651 , H01L2225/06537 , H01L2225/06568 , H01L2924/00 , H01L2924/00014 , H01L2924/10162 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.
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公开(公告)号：US20170309585A1
公开(公告)日：2017-10-26
申请号：US15645560
申请日：2017-07-10
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yi-Cheih Chen , Sung-Huan Sun , Cheng-An Chang , Chien-Hung Wu , Fu-Tang Huang
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0231 , H01L2224/03019 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/03916 , H01L2224/0401 , H01L2224/05024 , H01L2224/05166 , H01L2224/05647 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11474 , H01L2224/1148 , H01L2224/11849 , H01L2224/119 , H01L2224/11916 , H01L2224/13007 , H01L2224/13024 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2924/014 , H01L2924/00014
Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
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公开(公告)号：US09735124B2
公开(公告)日：2017-08-15
申请号：US14957027
申请日：2015-12-02
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yi-Cheih Chen , Sung-Huan Sun , Cheng-An Chang , Chien-Hung Wu , Fu-Tang Huang
CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0231 , H01L2224/03019 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/03916 , H01L2224/0401 , H01L2224/05024 , H01L2224/05166 , H01L2224/05647 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11474 , H01L2224/1148 , H01L2224/11849 , H01L2224/119 , H01L2224/11916 , H01L2224/13007 , H01L2224/13024 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2924/014 , H01L2924/00014
Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
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公开(公告)号：US09524944B2
公开(公告)日：2016-12-20
申请号：US15143691
申请日：2016-05-02
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chun-Wei Yeh , Chun-Hsien Shen , Hsiu-Jung Li , Ya-Yi Lai , Fu-Tang Huang
IPC: H01L21/44 , H01L21/4763 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/00 , H01L23/31 , H01L23/525
CPC classification number: H01L24/05 , H01L23/3114 , H01L23/3192 , H01L23/525 , H01L23/562 , H01L24/03 , H01L24/13 , H01L2224/02351 , H01L2224/02375 , H01L2224/0345 , H01L2224/03462 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05022 , H01L2224/05027 , H01L2224/05569 , H01L2224/05572 , H01L2224/1134 , H01L2224/11849 , H01L2224/13006 , H01L2224/13026 , H01L2224/131 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/00012 , H01L2924/014
Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion d having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.
Abstract translation: 公开了一种封装结构，其包括具有主体的基板，形成在主体上的多个导电焊盘和形成在主体上的表面钝化层，并且具有用于暴露导电焊盘的多个开口; 形成在所述表面钝化层的开口中并电连接到所述导电焊盘的多个导电通孔; 形成在所述表面钝化层上并电连接到所述导电通孔的多个电路，其中所述电路具有多个电触点; 至少形成在所述表面钝化层上并且与所述电路相交的图案部分; 以及形成在表面钝化层上的第二钝化层，电路和图案部分d具有多个开口，用于暴露电路的电接触部分，从而加强电路和钝化层之间的接合。
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公开(公告)号：US20160247773A1
公开(公告)日：2016-08-25
申请号：US15143691
申请日：2016-05-02
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chun-Wei Yeh , Chun-Hsien Shen , Hsiu-Jung Li , Ya-Yi Lai , Fu-Tang Huang
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L23/3114 , H01L23/3192 , H01L23/525 , H01L23/562 , H01L24/03 , H01L24/13 , H01L2224/02351 , H01L2224/02375 , H01L2224/0345 , H01L2224/03462 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05022 , H01L2224/05027 , H01L2224/05569 , H01L2224/05572 , H01L2224/1134 , H01L2224/11849 , H01L2224/13006 , H01L2224/13026 , H01L2224/131 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/00012 , H01L2924/014
Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have, a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion d having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.
Abstract translation: 公开了一种封装结构，其包括具有主体的基板，形成在主体上的多个导电焊盘和形成在主体上的表面钝化层，并且具有用于暴露导电焊盘的多个开口; 形成在所述表面钝化层的开口中并电连接到所述导电焊盘的多个导电通孔; 形成在所述表面钝化层上并电连接到所述导电通路的多个电路，其中所述电路具有多个电触头; 至少形成在所述表面钝化层上并且与所述电路相交的图案部分; 以及形成在表面钝化层上的第二钝化层，电路和图案部分d具有多个开口，用于暴露电路的电接触部分，从而加强电路和钝化层之间的接合。
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Patent Agency Ranking
46.发明申请公开(公告)号：US20160099204A1
公开(公告)日：2016-04-07
申请号：US14709510
申请日：2015-05-12
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Chia-Cheng Chen , Chih-Jen Yang , Fu-Tang Huang
CPC classification number: H01L23/49838 , H01L23/3121 , H01L23/49811 , H01L23/49822 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/131 , H01L2224/14131 , H01L2224/14133 , H01L2224/16227 , H01L2224/16238 , H01L2224/17106 , H01L2224/81193 , H01L2224/81385 , H01L2224/81801 , H01L2924/18161 , H01L2924/381 , H01L2924/3841 , H05K1/111 , H05K2201/0367 , H05K2201/0376 , H05K2201/09227 , H05K2201/10674 , Y02P70/611 , H01L2924/014 , H01L2924/00014
Abstract: A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate.
Abstract translation: 提供一种封装结构，包括：具有多个导电迹线的板; 多个导电焊盘，其形成在所述板上并且每个具有高于每个所述导电迹线的高度的高度; 以及电子部件，其经由多个导电元件设置在导电焊盘上并与其电连接，其中至少一个导电迹线位于至少一个导电焊盘附近。 因此，防止了导电元件与导电迹线接触，解决了导电焊盘和导电迹线短路的问题。 本发明还提供一种制造封装基板的方法。
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公开(公告)号：US20150237717A1
公开(公告)日：2015-08-20
申请号：US14453977
申请日：2014-08-07
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-fu Lin Chang , Chin-Tsai Yao , Ming-Chin Chuang , Ko-Cheng Liu , Fu-Tang Huang
CPC classification number: H05K3/4644 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/181 , H05K1/02 , H05K1/0296 , H05K1/0298 , H05K1/181 , H05K3/284 , H05K2201/0191 , H05K2201/09736 , H05K2201/20 , H05K2203/0353 , H05K2203/0369 , H01L2924/00012 , H01L2924/00
Abstract: A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.
Abstract translation: 提供一种封装基板，其包括多个电介质层和与电介质层交替堆叠的多个电路层。 至少两个电路层的厚度不同，以防止基板翘曲。
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公开(公告)号：US20140191376A1
公开(公告)日：2014-07-10
申请号：US13855221
申请日：2013-04-02
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Fu-Tang Huang , Chun-Chi Ke
IPC: H01L23/552 , H01L21/02
CPC classification number: H01L23/552 , H01L21/56 , H01L23/3121 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/91 , H01L24/92 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/02379 , H01L2224/02381 , H01L2224/04026 , H01L2224/04042 , H01L2224/05548 , H01L2224/05554 , H01L2224/05567 , H01L2224/06133 , H01L2224/06135 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/48132 , H01L2224/48137 , H01L2224/48227 , H01L2224/48235 , H01L2224/49052 , H01L2224/49107 , H01L2224/49175 , H01L2224/73215 , H01L2224/73257 , H01L2224/73265 , H01L2224/92165 , H01L2224/92247 , H01L2225/0651 , H01L2225/06537 , H01L2225/06568 , H01L2924/00 , H01L2924/00014 , H01L2924/10162 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.
Abstract translation: 提供一种半导体封装，包括：基板; 第一半导体元件，其设置在所述基板上并具有与所述基板接地的第一导电焊盘; 导电层，其形成在所述第一半导体元件上并电连接到所述基板; 通过所述导电层设置在所述第一半导体元件上的第二半导体元件; 以及形成在所述基板上并封装所述第一和第二半导体元件的密封剂。 因此，第一和第二半导体元件被保护免受电磁干扰（EMI）屏蔽，导电层连接到衬底的接地衬垫。 还提供了半导体封装的制造方法。
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公开(公告)号：US20140183755A1
公开(公告)日：2014-07-03
申请号：US13872494
申请日：2013-04-29
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Fu-Tang Huang , Chun-Chi Ke
IPC: H01L23/552 , H01L21/58
CPC classification number: H01L23/552 , H01L21/76898 , H01L23/147 , H01L23/3121 , H01L23/49811 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/11002 , H01L2224/13025 , H01L2224/14181 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/24226 , H01L2224/245 , H01L2224/32225 , H01L2224/73204 , H01L2224/73259 , H01L2224/92125 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06537 , H01L2225/06541 , H01L2225/06568 , H01L2924/10253 , H01L2924/15311 , H01L2924/157 , H01L2924/181 , H01L2924/00012 , H01L2224/16145 , H01L2224/32145 , H01L2924/00 , H01L2224/11 , H01L2224/1403
Abstract: A semiconductor package is provided, which includes a carrier having a mounting area and at least a grounding pad; a substrate body having opposite first and second surfaces and a plurality of conductive vias each having a first end exposed from the first surface and a second end opposite to the first end, the substrate body being disposed on the mounting area of the carrier through the second surface thereof; a metal layer formed on the first surface of the substrate body and exposing the first ends of the conductive vias; a conductive body electrically connecting the metal layer and the grounding pad; and a semiconductor element disposed on the substrate body and electrically connected to the first ends of the conductive vias, thereby achieving an EMI shielding effect to prevent interference between electromagnetic waves or electrical signals of the substrate body and the semiconductor element.
Abstract translation: 提供一种半导体封装，其包括具有安装区域和至少接地焊盘的载体; 具有相对的第一和第二表面的衬底体和多个导电通孔，每个具有从第一表面暴露的第一端和与第一端相对的第二端，衬底主体通过第二表面设置在载体的安装区域上 表面 形成在所述基板主体的第一表面上并暴露所述导电通路的所述第一端的金属层; 电连接金属层和接地垫的导电体; 以及半导体元件，其设置在所述基板主体上并电连接到所述导电通孔的所述第一端，由此实现EMI屏蔽效果以防止所述基板主体和所述半导体元件的电磁波或电信号之间的干扰。
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公开(公告)号：US20140021629A1
公开(公告)日：2014-01-23
申请号：US13654754
申请日：2012-10-18
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Chiang-Cheng Chang , Meng-Tsung Lee , Jung-Pang Huang , Shih-Kuang Chiu , Fu-Tang Huang
CPC classification number: H01L21/568 , H01L21/561 , H01L21/6835 , H01L21/76802 , H01L21/76834 , H01L21/76877 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2221/68318 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05567 , H01L2224/12105 , H01L2224/131 , H01L2224/24153 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.
Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。
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