公开(公告)号：US07737528B2

公开(公告)日：2010-06-15

申请号：US12132337

申请日：2008-06-03

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

IPC分类号： H01L21/768

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.

摘要翻译： 用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层; 仅在所述金属互连层的顶表面的一部分上形成的金属盖层; 以及形成在所述金属盖层和所述金属互连层的其余部分上的电介质盖层，其不形成有所述金属盖层; 其中不具有形成在其上的金属覆盖层的金属互连层的其余部分容易受到电迁移故障机制的影响，以便通过施加通过细长金属互连层的电流来编程熔丝结构。

公开(公告)号：US07732845B2

公开(公告)日：2010-06-08

申请号：US12099339

申请日：2008-04-08

申请人： James W Adkisson ,  Jeffrey P. Gambino ,  Rajendran Krishnasamy ,  Solomon Mulugeta

发明人： James W Adkisson ,  Jeffrey P. Gambino ,  Rajendran Krishnasamy ,  Solomon Mulugeta

IPC分类号： H01L31/062

CPC分类号： H01L27/14603

摘要： A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region.

摘要翻译： 在CMOS图像传感器的栅电极上方形成拉伸应力产生结构，以在也是转移晶体管的源极区域的光电二极管的电荷收集阱和浮动漏极之间施加正常的拉伸应力 连接源极区域和浮动漏极的方向。 拉伸应力降低了源区域和转移晶体管的主体之间的势垒，以实现更快和更多地将源区域中的电荷转移到浮动漏极。 因此CMOS图像传感器中的图像滞后减少。 此外，由于施加到源极区域的正常拉伸应力，源极区域的充电容量也增强​​。

公开(公告)号：US07682961B2

公开(公告)日：2010-03-23

申请号：US11422979

申请日：2006-06-08

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： In a first aspect, a method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.

摘要翻译： 在第一方面，一种方法包括将第一含金属层沉积到与半导体结构的金属化区域接触的沟槽结构中。 该方法还包括将抗蚀剂中的至少一个开口图案化为第一含金属层。 开口应与沟槽结构对齐。 在至少一个开口内（优选通过电镀工艺）形成至少一垫层金属层。 然后蚀刻抗蚀剂和抗蚀剂下面的第一金属层（在实施例中第二金属层用作掩模）。 该方法包括在蚀刻工艺之后使沟槽内的焊料材料和含焊垫金属的层流动。 该结构是受控的崩溃芯片连接（C4）结构，包括至少一个以抗蚀剂图案形成的电镀金属层，以形成至少一个球限制冶金层。 该结构还包括没有底切的底层金属层。

公开(公告)号：US07655495B2

公开(公告)日：2010-02-02

申请号：US11623977

申请日：2007-01-17

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，具有改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

公开(公告)号：US20090283807A1

公开(公告)日：2009-11-19

申请号：US12120413

申请日：2008-05-14

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

IPC分类号： H01L31/0232

CPC分类号： H01L31/103 ,  H01L24/05 ,  H01L24/73 ,  H01L27/14603 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1464 ,  H01L27/14643 ,  H01L31/02165 ,  H01L31/0236 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  Y02E10/50 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

摘要翻译： 提供了具有不同折射率的两层之间的突起阵列的光学结构。 突起阵列具有小于由CMOS图像传感器的光电二极管可检测的光的波长范围的垂直和侧向尺寸。 突起的阵列提供了很少的反射光的高透射率。 突起阵列可以设置在光电二极管上，后端行互连结构中，用于光电二极管的透镜，光电二极管的背面或芯片封装的窗口上。

公开(公告)号：US20090280631A1

公开(公告)日：2009-11-12

申请号：US12117769

申请日：2008-05-09

申请人： Jeffrey P. Gambino ,  Michael P. Chudzik ,  Renee T. Mo

发明人： Jeffrey P. Gambino ,  Michael P. Chudzik ,  Renee T. Mo

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.

摘要翻译： 本发明在一个实施例中提供了一种形成半导体器件的方法，包括提供包括半导体表面的衬底，该衬底包括第一器件区域和第二器件区域; 在衬底的半导体表面上方形成高k电介质层; 在所述衬底的所述第二器件区域的顶部形成掩模掩模，其中所述衬底的所述第一器件区域被暴露; 在存在于所述衬底的第一器件区域中的高k电介质层的顶部形成第一金属层; 去除所述块掩模以暴露所述衬底的所述第一器件区域中的所述高k电介质层的一部分; 在所述第二器件区域中的所述高k电介质层的所述部分的顶部上形成第二金属层，并且在所述衬底的所述第一器件区域中的所述第一金属顶上形成第二金属层; 以及在所述衬底的所述第一和第二器件区域中形成栅极结构。

公开(公告)号：US07545050B1

公开(公告)日：2009-06-09

申请号：US12183369

申请日：2008-07-31

申请人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

发明人： Timothy Harrison Daubenspeck ,  Wolfgang Sauter ,  Jeffrey P. Gambino ,  David L. Questad

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05655 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.

摘要翻译： 提供用于半导体芯片的封装的设计结构，其使从芯片到衬底或芯片到卡互连的差分热膨胀产生的应力和应变最小化。 在最终铜金属化水平之上的一组改进的设计结构通孔，可减轻半导体组装和测试期间的冲击。 其他实施例包括具有变化的微机械支撑结构的设计结构，其进一步最小化半导体封装中的应力和应变。

公开(公告)号：US07521798B2

公开(公告)日：2009-04-21

申请号：US11943277

申请日：2007-11-20

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC分类号： H01L23/48

CPC分类号： H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20090085152A1

公开(公告)日：2009-04-02

申请号：US11865079

申请日：2007-10-01

申请人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

发明人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

IPC分类号： H01L23/62 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

摘要翻译： 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。

公开(公告)号：US07500208B2

公开(公告)日：2009-03-03

申请号：US11673369

申请日：2007-02-09

申请人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

发明人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

IPC分类号： G06F17/50 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

摘要翻译： 用于评估半导体集成电路中的线路的新型结构和方法。 在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有部分的电阻来确定第一行几何调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。