公开(公告)号：US06927471B2

公开(公告)日：2005-08-09

申请号：US10237640

申请日：2002-09-06

Applicant: Peter C. Salmon

Inventor： Peter C. Salmon

IPC: H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H05K3/46 ,  H01L29/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/16 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/25 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4682 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/20751 ,  H01L2924/00

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括轨迹宽度为5微米或更小的柔性多层互连电路。 用于制造液晶显示器，LCD，面板的玻璃面板制造设备用于制造互连电路。 在具有中间剥离层的玻璃载体上形成聚合物基层。 金属和电介质的交替层形成在基底层上，并被图案化以在玻璃面板上产生多层互连电路阵列。 在互连电路上沉积一层聚合物，并在输入/输出（I / O）焊盘位置形成开口。 将焊膏沉积在开口中以形成填充有焊料的孔。 在切割玻璃载体以形成分离的互连电路之后，使用倒装芯片接合对IC芯片进行螺柱凸起并组装，其中部件上的螺柱凸起插入到互连电路上的对应的孔中。 对IC芯片进行测试和返工以形成测试电路组件。 描述了连接到测试仪和其他模块和电子系统的方法。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器实施例。

公开(公告)号：US20050157447A1

公开(公告)日：2005-07-21

申请号：US10895113

申请日：2004-07-21

Applicant: Uei-Ming Jow ,  Chin-Sun Shyu

Inventor： Uei-Ming Jow ,  Chin-Sun Shyu

IPC: H01G4/012 ,  H01G4/228 ,  H01G17/00 ,  H05K1/16

CPC classification number: H01G4/012 ,  H01G4/228 ,  H05K1/162 ,  H05K2201/09509 ,  H05K2201/09672

Abstract: A structure and method for manufacturing multi-electrode capacitor within a PCB is used to form a multi-electrode capacitor with a plurality of metal laminates coupled each other and employing the characteristics of the edge-coupled effect therein. the present invention can provide efficient capacitance from the capacitor with the smallest area. The present invention is applied to promote the capability of noise-restraint of the capacitive substrate in a high-frequency/speed system, and further achieves the purpose of regular circuit design with the smallest area in the future development.

Abstract translation: 使用用于在PCB内制造多电极电容器的结构和方法来形成具有彼此耦合的多个金属层压体的多电极电容器，并且采用其中的边缘耦合效应的特性。 本发明可以从具有最小面积的电容器提供有效的电容。 本发明应用于提​​高高频/速度系统中电容基板的噪声抑制能力，进一步达到将来开发面积最小的规则电路设计的目的。

公开(公告)号：US20050146858A1

公开(公告)日：2005-07-07

申请号：US10969861

申请日：2004-10-22

Applicant: Noboru Nishida

Inventor： Noboru Nishida

IPC: G06K19/077 ,  H05K1/00 ,  H05K1/11 ,  H05K3/46 ,  H05K5/00

CPC classification number: H05K1/117 ,  H05K1/0298 ,  H05K2201/09481 ,  H05K2201/09509

Abstract: A card-type electronic device has a multilayer printed wiring board and a case which houses the multilayer printed wiring board. The case has an opening. The multilayer printed wiring board includes a plurality of insulating layers and a plurality of conductive layers, which are alternately stacked, and has a flat surface on one side thereof along a stacked direction. The flat surface is formed of one of the insulating layers, and at least a part of the flat surface is exposed to the outside of the case through the opening.

Abstract translation: 卡式电子设备具有多层印刷线路板和容纳多层印刷线路板的壳体。 案件有一个开场。 多层印刷线路板包括交替堆叠的多个绝缘层和多个导电层，并且沿堆叠方向在其一侧具有平坦表面。 平坦表面由绝缘层之一形成，并且平坦表面的至少一部分通过开口暴露于外壳的外部。

公开(公告)号：US20050133251A1

公开(公告)日：2005-06-23

申请号：US11015683

申请日：2004-12-17

Applicant: Chi-Tsung Chiu

Inventor： Chi-Tsung Chiu

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/40

CPC classification number: H05K1/115 ,  H05K1/0237 ,  H05K3/0038 ,  H05K3/027 ,  H05K3/403 ,  H05K2201/0347 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/09645

Abstract: A substrate to which a laser technique is applied includes a signal layer, a micro via structure, and a differential signal pair. The micro via structure is divided into a first conductive column and a second conductive column after a laser-cutting step. The first conductive column includes a first flat conductive layer, and the second conductive column includes a second flat conductive layer. A first trace of the differential signal pair is parallel to and electrically connected to the first flat conductive layer. A second trace of the differential signal pair is parallel to and electrically connected to the second flat conductive layer. The distance between the first trace and the second trace is the same as the distance between the first flat conductive layer and the second flat conductive layer. The reflection of high-speed signals and the noise interferences can be reduced.

Abstract translation: 应用激光技术的基板包括信号层，微通孔结构和差分信号对。 微通孔结构在激光切割步骤之后被分成第一导电柱和第二导电柱。 第一导电柱包括第一平坦导电层，第二导电柱包括第二平坦导电层。 差分信号对的第一迹线平行于并电连接到第一平坦导电层。 差分信号对的第二迹线平行于并电连接到第二平坦导电层。 第一迹线和第二迹线之间的距离与第一平坦导电层和第二平坦导电层之间的距离相同。 可以降低高速信号的反射和噪声干扰。

公开(公告)号：US20050121225A1

公开(公告)日：2005-06-09

申请号：US10876476

申请日：2004-06-28

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H05K3/28 ,  H05K3/38 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K3/462 ,  H05K3/28 ,  H05K3/381 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/095 ,  Y10T29/49126

Abstract: A multi-layer circuit board and a method for fabricating the same are proposed. A plurality of circuit board units are prepared and formed with patterned circuit layers thereon. At least one insulating layer is formed on each of the circuit board units. The insulating layer is patterned to form a plurality of opening or is thinned to expose contact pads of the circuit layers on the circuit board units. The circuit board units undergo surface activation and laminating processes in vacuum to form a multi-layer circuit board, wherein the circuit board units are laminated and electrically connected together by the exposed contact pads. This method reduces the time and cost for fabrication.

Abstract translation: 提出了一种多层电路板及其制造方法。 制备多个电路板单元并在其上形成图案化的电路层。 在每个电路板单元上形成至少一个绝缘层。 图案化绝缘层以形成多个开口或被稀释以暴露电路板单元上的电路层的接触焊盘。 电路板单元在真空中进行表面活化和层压工艺以形成多层电路板，其中电路板单元通过暴露的接触垫层压并电连接在一起。 这种方法减少了制造的时间和成本。

公开(公告)号：US20050104191A1

公开(公告)日：2005-05-19

申请号：US10713804

申请日：2003-11-14

Applicant: Uei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Pei-Shen Wei ,  Ching-Liang Weng ,  Chun-Kun Wu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

IPC: H01L21/4763 ,  H01L23/053 ,  H01L23/48 ,  H05K1/02 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K1/0218 ,  H05K1/0219 ,  H05K3/4602 ,  H05K2201/0723 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09672

Abstract: An embedded microelectronic capacitor incorporating at least one ground shielding layer is provided which includes an upper ground shielding layer that has an aperture therethrough; an electrode plate positioned spaced-apart from the upper ground shielding layer that has a via extending upwardly away from the electrode plate through the aperture in the upper ground shielding layer providing electrical communication to the electrode plate without shorting to the upper ground shielding layer; a middle ground shielding layer positioned in the same plane of the electrode plate, surrounding while spaced-apart from the electrode plate at a predetermined distance; a lower ground shielding layer positioned spaced-apart from the electrode plate in an opposing relationship to the upper ground shielding layer; and a dielectric material embedding the upper ground shielding layer; the middle ground shielding layer and the lower ground shielding layer.

公开(公告)号：US06847527B2

公开(公告)日：2005-01-25

申请号：US10199926

申请日：2002-07-19

Applicant: Mark F. Sylvester ,  David A. Hanson ,  William G. Petefish

Inventor： Mark F. Sylvester ,  David A. Hanson ,  William G. Petefish

IPC: H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H01L23/66 ,  H05K1/11 ,  H05K1/14 ,  H05K1/16 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06 ,  H05K1/03

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/66 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/141 ,  H05K1/162 ,  H05K3/0035 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0112 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/049 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10734 ,  H05K2203/1383 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/81205

Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract translation: 用于集成电路芯片的互连模块结合了薄的高介电常数嵌入式电容器结构，以提供降低的功率分布阻抗，从而促进更高频率的操作。 互连模块能够通过焊球连接将集成电路芯片可靠地附接到印刷线路板，同时在超过1.0千兆赫的工作频率下提供小于或等于约0.60欧姆的降低的功率分布阻抗。

公开(公告)号：US06846993B2

公开(公告)日：2005-01-25

申请号：US10267788

申请日：2002-10-10

Applicant: Isao Matsui

Inventor： Isao Matsui

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01R12/04

CPC classification number: H05K1/0271 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/0969 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A conductive film has a plurality of clearances (openings) and a plurality of auxiliary clearances. The plurality of clearances and the plurality of auxiliary clearances are formed to have such numerical apertures and locations that generate no bias in the distribution of conductive film in consideration of the entire conductive film. The conductive film can disperse stress caused by thermal expansion etc., to ease by having the plurality of clearances and the plurality of auxiliary clearances. Accordingly, the conductive film is less prone to being peeled off the insulating film. Further, since the distribution of conductive film is substantially uniform as a whole, the transfer characteristics that are fixed by the distribution become substantially uniform as a whole.

Abstract translation: 导电膜具有多个间隙（开口）和多个辅助间隙。 考虑到整个导电膜，多个间隙和多个辅助间隙形成为具有在导电膜的分布中不产生偏置的数值孔径和位置。 导电膜可以分散由热膨胀等引起的应力，以便通过具有多个间隙和多个辅助间隙来简化。 因此，导电膜不容易从绝缘膜剥离。 此外，由于导电膜的分布总体上基本上是均匀的，因此通过分布固定的转印特性总体上基本上是均匀的。

公开(公告)号：US20050005436A1

公开(公告)日：2005-01-13

申请号：US10615139

申请日：2003-07-09

Applicant: Jung-Chien Chang

Inventor： Jung-Chien Chang

IPC: H05K3/20 ,  H05K3/28 ,  H05K3/40 ,  H05K3/46 ,  B05D5/12

CPC classification number: H05K3/4007 ,  H05K3/205 ,  H05K3/284 ,  H05K3/4652 ,  H05K2201/09045 ,  H05K2201/09509 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49155

Abstract: A method for preparing thin integrated circuits having multiple circuit layers has the following acts of: forming a first circuit layer on a substrate; depositing at least one resin and copper layer on the first circuit layer; forming a second circuit layer on the at least one resin and copper layer; electrically connecting the first and second circuit layers; attaching electronic components to the first or second circuit layers; applying an encapsulant layer to protect the electronic components; and removing the substrate to expose the first circuit layer. By removing the substrate, the integrated circuit is much thinner.

Abstract translation: 一种制备具有多个电路层的薄集成电路的方法具有以下动作：在衬底上形成第一电路层; 在所述第一电路层上沉积至少一个树脂和铜层; 在所述至少一个树脂和铜层上形成第二电路层; 电连接第一和第二电路层; 将电子部件附接到所述第一或第二电路层; 施加密封剂层以保护电子部件; 以及去除所述衬底以暴露所述第一电路层。 通过去除衬底，集成电路要薄得多。

公开(公告)号：US20040251046A1

公开(公告)日：2004-12-16

申请号：US10461840

申请日：2003-06-13

Applicant: ITT Manufacturing Enterprises, Inc.

Inventor： Scott Keith Mickievicz ,  John Edward Knaub

IPC: H05K001/18

CPC classification number: H05K3/4623 ,  H05K1/112 ,  H05K3/3421 ,  H05K3/4614 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10704

Abstract: Tails (20) projecting from an electrical component (12) that lies on a circuit board surface, are terminated to traces on a multi-layer circuit board (14) in a manner that minimizes the disadvantages of long through hole soldering and of surface mount techniques. A blind hole is drilled and plated in a first layer (31) that will become the topmost layer of the stack, to form a shallow well (70). The well is filled with a soldering composition (130). A tail (20) is projected downward into the soldering composition, and the soldering composition is heated to solder the tail to the hole plating.

Abstract translation: 从位于电路板表面的电气部件（12）突出的尾部（20）以多层电路板（14）的迹线端接，以最小化长通孔焊接和表面安装的缺点 技术 钻一个盲孔并镀在将成为堆叠的最上层的第一层（31）中以形成浅井（70）。 该井装有焊接组合物（130）。 尾部（20）向下突出到焊接组合物中，并且焊接组合物被加热以将尾部焊接到孔镀层。