公开(公告)号：US20070210439A1

公开(公告)日：2007-09-13

申请号：US11715906

申请日：2007-03-09

Applicant: Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad. The board on chip package and the manufacturing method thereof according to the present invention can design a high density circuit since a circuit pattern is formed using a seed layer.

Abstract translation: 本发明的一个方面的特征在于片上封装的制造方法。 该方法可以包括：（a）在载体膜上层压干膜，其一面由薄金属膜层压; （b）通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; （c）去除干膜; （d）层压除了形成焊锡球焊盘的部分之外的上光阻焊剂; （e）蚀刻形成在上层光阻抗层未层叠的部分上的金属薄膜; （f）通过倒装芯片接合将半导体芯片安装在焊球垫上; （g）用钝化材料模制半导体芯片; （h）去除载体膜和金属薄膜; 和（i）在焊球垫下方层叠下光阻焊剂。 根据本发明的片上封装及其制造方法可以设计高密度电路，因为使用种子层形成电路图案。

公开(公告)号：US20070120253A1

公开(公告)日：2007-05-31

申请号：US11602332

申请日：2006-11-21

Applicant: Yoong Oh ,  Chang-Sup Ryu ,  Dong-Jin Park ,  Jee-Soo Mok ,  Byung-Bae Seo

Inventor： Yoong Oh ,  Chang-Sup Ryu ,  Dong-Jin Park ,  Jee-Soo Mok ,  Byung-Bae Seo

IPC: H01L23/48

CPC classification number: H01L21/486 ,  H01L21/4867 ,  H01L23/49827 ,  H01L23/49883 ,  H01L2924/0002 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2203/063 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A core substrate and multilayer printed circuit board using paste bumps and manufacturing method thereof are disclosed. With the method of manufacturing a core substrate using paste bumps comprising: (a) aligning a pair of paste bump boards, each of which has a plurality of paste bumps joined to its surface, such that the paste bumps face each other, and (b) pressing the pair of paste bump boards together, where an insulation element is placed between the pair of paste bump boards, it is easier to implement interlayer electrical interconnection between circuit patterns, the thickness of the core substrate can readily be adjusted by adjusting the thickness of the insulation layer, the stiffness is improved as a pair of paste bump boards are pressed from the top and bottom, and high-density wiring can be formed more easily as the paste bumps are connected in pairs so that the diameters of the paste bumps formed on the paste bump boards can be reduced.

Abstract translation: 公开了一种使用糊状凸块的芯基板和多层印刷电路板及其制造方法。 利用使用糊状凸块的芯基板的制造方法，其特征在于，包括：（a）对准一对粘贴凸块，其中，每一个均具有与其表面接合的多个焊料凸块，使得所述焊膏凸起彼此面对;以及（b ）将一对焊膏凸块按压在一起，其中绝缘元件放置在一对焊膏凸块之间，更容易实现电路图案之间的层间电互连，通过调节厚度可以容易地调节芯基板的厚度 的绝缘层，由于从顶部和底部按压一对糊状凸块，刚度得以改善，并且随着糊料凸块成对连接，可以更容易地形成高密度布线，使得糊料凸块的直径 可以减少形成在糊状凸块上。

公开(公告)号：US20060044734A1

公开(公告)日：2006-03-02

申请号：US10999442

申请日：2004-11-29

Applicant: Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

Inventor： Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

IPC: H01G4/20

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/1218 ,  H01G4/248 ,  H01G4/33 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1366 ,  Y10T29/42

Abstract: Disclosed is a PCB including embedded capacitors and a method of fabricating the same. A dielectric layer is formed using a ceramic material having a high capacitance, thereby assuring that the capacitors each have a high dielectric constant corresponding to the capacitance of a decoupling chip capacitor.

Abstract translation: 公开了一种包括嵌入式电容器的PCB及其制造方法。 使用具有高电容的陶瓷材料形成电介质层，从而确保电容器各自具有对应于去耦芯片电容器的电容的高介电常数。

公开(公告)号：US08966746B2

公开(公告)日：2015-03-03

申请号：US13064847

申请日：2011-04-20

Applicant: Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

Inventor： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

IPC: H05K3/30 ,  H05K1/16 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09563 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of fabricating a cavity capacitor embedded in a printed circuit board including two conductive layers to be used as a power layer and a ground layer, respectively, and a first dielectric layer, placed between the two conductive layers, the method including: removing an upper conductive layer and the first dielectric layer excluding a lower conductive layer of the two conductive layers to allow a cavity to be formed between the two conductive layers, the lower conductive layer being supposed to be used as any one of electrodes of the cavity capacitor; stacking a dielectric material on the cavity to allow a second dielectric layer having a lower stepped portion than the first dielectric layer to be formed in the cavity; and stacking a conductive material on an upper part of the second dielectric layer and side parts of the cavity to allow the upper conductive layer to be used as the other electrode of the cavity capacitor.

Abstract translation: 一种嵌入在印刷电路板中的空腔电容器的方法，包括分别用作功率层和接地层的两个导电层和放置在两个导电层之间的第一介电层，所述方法包括： 上导电层和除了两个导电层的下导电层之外的第一电介质层，以允许在两个导电层之间形成腔，下导电层假定用作空腔电容器的任一电极; 在所述空腔上堆叠电介质材料以允许在所述空腔中形成具有比所述第一电介质层更低的台阶部分的第二电介质层; 并且在第二电介质层的上部和空腔的侧部上堆叠导电材料，以允许上部导电层用作空腔电容器的另一个电极。

公开(公告)号：US08592135B2

公开(公告)日：2013-11-26

申请号：US13403380

申请日：2012-02-23

Applicant: Jee Soo Mok ,  Je Gwang Yoo ,  Eung Suek Lee ,  Chang Sup Ryu

Inventor： Jee Soo Mok ,  Je Gwang Yoo ,  Eung Suek Lee ,  Chang Sup Ryu

IPC: G03F7/26

CPC classification number: H05K3/4007 ,  B82Y10/00 ,  H05K1/095 ,  H05K2201/026 ,  H05K2201/0367 ,  H05K2203/0514

Abstract: A method of manufacturing a printed circuit board, including: applying a conductive paste including carbon nanotubes and a photosensitive binder on a bump-forming area of a circuit substrate having a circuit layer for transferring electrical signals; and patterning the conductive paste, thus forming bumps.

Abstract translation: 一种制造印刷电路板的方法，包括：在具有用于传送电信号的电路层的电路基板的凸起形成区域上涂覆包括碳纳米管和感光性粘合剂的导电浆料; 并图案化导电膏，从而形成凸块。

公开(公告)号：US08499444B2

公开(公告)日：2013-08-06

申请号：US12216152

申请日：2008-06-30

Applicant: Jin-Yong An ,  Chang-Sup Ryu ,  Jong-Kuk Hong

Inventor： Jin-Yong An ,  Chang-Sup Ryu ,  Jong-Kuk Hong

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K1/02 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0097 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T428/24851 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A package substrate and a method of manufacturing the package substrate are disclosed. The method of manufacturing the package substrate may include stacking a second metal layer in which at least one hole is formed over a first metal layer, stacking a barrier layer over the first metal layer exposed in the hole and over the second metal layer, forming at least one bump by filling the hole with a conductive metal, stacking an insulation layer over the bump and forming a circuit pattern over the insulation layer, and removing the first metal layer, the second metal layer, and the barrier layer.

Abstract translation: 公开了封装基板和制造封装基板的方法。 制造封装衬底的方法可以包括堆叠第二金属层，其中在第一金属层上形成至少一个孔，在第一金属层上方在第二金属层上方堆叠阻挡层，形成在第二金属层上 通过用导电金属填充所述孔至少一个凸块，在所述凸块上方堆叠绝缘层并在所述绝缘层上形成电路图案，以及去除所述第一金属层，所述第二金属层和所述阻挡层。

公开(公告)号：US08232478B2

公开(公告)日：2012-07-31

申请号：US12654766

申请日：2009-12-31

Applicant: Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

Inventor： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

IPC: H05K9/00

CPC classification number: H05K9/0071 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0236 ,  H05K9/002 ,  H05K9/0064 ,  H05K2201/09309 ,  H05K2201/09627 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An EMI noise reduction board using an electromagnetic bandgap structure is disclosed. In the EMI noise reduction board according to an embodiment of the present invention, an electromagnetic bandgap structure having band stop frequency properties can be inserted into an inner portion of the board so as to shield an EMI noise, in which the portion corresponds to an edge of the board and in which the EMI noise is conducted from the inside to the edge of the board and radiates to the outside of the board.

Abstract translation: 公开了一种使用电磁带隙结构的EMI降噪板。 在根据本发明实施例的EMI噪声抑制板中，具有带阻频率特性的电磁带隙结构可以插入到板的内部，以屏蔽EMI噪声，其中该部分对应于边缘 并且其EMI噪声从板的内部传导到边缘并辐射到板的外部。

公开(公告)号：US20120148960A1

公开(公告)日：2012-06-14

申请号：US13403380

申请日：2012-02-23

Applicant: Jee Soo Mok ,  Je Gwang Yoo ,  Eung Suek Lee ,  Chang Sup Ryu

Inventor： Jee Soo Mok ,  Je Gwang Yoo ,  Eung Suek Lee ,  Chang Sup Ryu

IPC: G03F7/20 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: H05K3/4007 ,  B82Y10/00 ,  H05K1/095 ,  H05K2201/026 ,  H05K2201/0367 ,  H05K2203/0514

Abstract: A method of manufacturing a printed circuit board, including: applying a conductive paste including carbon nanotubes and a photosensitive binder on a bump-forming area of a circuit substrate having a circuit layer for transferring electrical signals; and patterning the conductive paste, thus forming bumps.

Abstract translation: 一种制造印刷电路板的方法，包括：在具有用于传送电信号的电路层的电路基板的凸起形成区域上涂覆包括碳纳米管和感光性粘合剂的导电浆料; 并图案化导电膏，从而形成凸块。

公开(公告)号：US08198550B2

公开(公告)日：2012-06-12

申请号：US12385003

申请日：2009-03-27

Applicant: Jee Soo Mok ,  Je Gwang Yoo ,  Chang Sup Ryu

Inventor： Jee Soo Mok ,  Je Gwang Yoo ,  Chang Sup Ryu

IPC: H01R12/04

CPC classification number: H05K3/4069 ,  H05K3/06 ,  H05K3/107 ,  H05K3/28 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2203/0278 ,  H05K2203/1461 ,  Y10T29/49144 ,  Y10T29/49155

Abstract: A printed circuit board and a method of manufacturing the printed circuit board, in which the printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer and having a connection pad that is embedded in the insulating layer such that one side of the connection pad is flush with a surface of the insulating layer, and insulating materials configured to protect the circuit layer from an external environment and having an opening through which the connection pad is exposed. The manufacturing process includes a step of pressing the circuit layer and the insulating material into the insulating layer to form a level surface while leaving the connection pads flush at the surface. The method makes the printed circuit board slim, and increases reliability and the degree of design freedom.

Abstract translation: 一种印刷电路板和印刷电路板的制造方法，其中印刷电路板包括绝缘层，嵌入绝缘层中的电路层，并且具有嵌入在绝缘层中的连接焊盘，使得 所述连接垫与所述绝缘层的表面齐平，以及被配置为保护所述电路层免受外部环境并且具有所述连接焊盘暴露的开口的绝缘材料。 该制造方法包括将电路层和绝缘材料压入绝缘层中以形成水平表面，同时使连接垫在表面平齐的步骤。 该方法使印刷电路板变薄，提高了可靠性和设计自由度。

公开(公告)号：US20120073865A1

公开(公告)日：2012-03-29

申请号：US13311058

申请日：2011-12-05

Applicant: Myung Sam Kang ,  Byoung Youl Min ,  Je Gwang Yoo ,  Jung Hyun Park ,  Chang Sup Ryu ,  Jin Yong Ahn

Inventor： Myung Sam Kang ,  Byoung Youl Min ,  Je Gwang Yoo ,  Jung Hyun Park ,  Chang Sup Ryu ,  Jin Yong Ahn

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H05K3/428 ,  H05K3/205 ,  H05K3/383 ,  H05K3/384 ,  H05K3/4602 ,  H05K3/4658 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/1536 ,  Y10T29/49155

Abstract: A carrier member for transmitting circuits, which is a component of a coreless printed circuit board having circuit patterns embedded therein, and which can be used to provide a high-density and highly reliable printed circuit board by forming protrusions only on the lower ends of the circuit patterns, a coreless printed circuit board using the carrier member, and methods of manufacturing the carrier member and the coreless printed circuit board.

Abstract translation: 用于发送电路的载体构件，其是具有嵌入其中的电路图案的无芯型印刷电路板的部件，并且其可用于通过仅在其下端形成突起来提供高密度和高可靠性的印刷电路板 电路图案，使用承载构件的无芯印刷电路板，以及制造载体构件和无芯非印刷电路板的方法。