公开(公告)号：US20120068359A1

公开(公告)日：2012-03-22

申请号：US13320798

申请日：2010-05-18

申请人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

发明人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00

摘要： A semiconductor device comprises: a core substrate; at least one insulating layer and at least one wiring layer which are disposed on each of a first surface of the core substrate and a second surface opposite to the first surface; a via(s) which is disposed in each of the insulating layer and the core substrate, and connects the wiring layers to each other; a semiconductor element, mounted on the first surface of the core substrate, with a surface for forming an electrode terminal(s) facing up; and a connecting portion(s) which penetrates the insulating layer disposed on the first surface and directly connects the electrode terminal of the semiconductor element and the wiring layer disposed on the first surface. A minimum wiring pitch of the wiring layer directly connected to the connecting portion is smaller than that of any of the wiring layer(s) disposed on the second surface.

摘要翻译： 半导体器件包括：芯基板; 至少一个绝缘层和至少一个布线层，其布置在所述芯基板的第一表面和与所述第一表面相对的第二表面中的每一个上; 布置在所述绝缘层和所述芯基板的每一个中的通孔，并且将所述布线层彼此连接; 半导体元件，安装在所述芯基板的第一表面上，具有用于形成面向上的电极端子的表面; 以及穿过设置在第一表面上的绝缘层的直接连接半导体元件的电极端子和布置在第一表面上的布线层的连接部分。 直接连接到连接部分的布线层的最小布线间距小于布置在第二表面上的布线层中的布线层的最小布线间距。

公开(公告)号：US08072073B2

公开(公告)日：2011-12-06

申请号：US12210702

申请日：2008-09-15

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/05 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/29099 ,  H01L2924/00

摘要： A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate; a first wiring structure placed on the semiconductor substrate and having one or more first wiring layers, one or more insulating layers and a first via; a second wiring structure placed on the first wiring structure and having one or more second wiring layers, one or more second insulating layers, a second via and a third via; and an external terminal provided on the second wiring structure. The second via, which is connected to the second wiring layer of the second wiring structure and to the external terminal, has a connection interface disposed at an end of the via that is on the side of the external terminal.

摘要翻译： 在非常小的通孔中确保连接可靠性的高度可靠的半导体器件包括：半导体衬底; 放置在半导体衬底上并具有一个或多个第一布线层，一个或多个绝缘层和第一通孔的第一布线结构; 放置在第一布线结构上并具有一个或多个第二布线层，一个或多个第二绝缘层，第二通孔和第三通孔的第二布线结构; 以及设置在第二布线结构上的外部端子。 连接到第二布线结构的第二布线层和外部端子的第二通孔具有布置在位于外部端子一侧的通孔的端部处的连接接口。

公开(公告)号：US08004074B2

公开(公告)日：2011-08-23

申请号：US12102414

申请日：2008-04-14

申请人： Kentaro Mori ,  Katsumi Kikuchi ,  Shintaro Yamamichi

发明人： Kentaro Mori ,  Katsumi Kikuchi ,  Shintaro Yamamichi

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device, in which a semiconductor element is mounted on one side of a circuit board that is made up from an insulating layer and a wiring layer, includes metal posts provided on the side of the circuit board on which the semiconductor element is mounted; and a sealing layer provided on the side of the circuit board on which the semiconductor element is mounted such that the semiconductor element is covered and such that only portions of the metal posts are exposed.

摘要翻译： 一种半导体器件，其中半导体元件安装在由绝缘层和布线层构成的电路板的一侧上，包括设置在其上安装有半导体元件的电路板侧的金属柱; 以及密封层，设置在电路板的安装半导体元件的侧面上，使得半导体元件被覆盖，并且仅使金属柱的一部分露出。

公开(公告)号：US07791186B2

公开(公告)日：2010-09-07

申请号：US11542261

申请日：2006-10-04

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

IPC分类号： H01L23/12

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2201/0989 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

摘要翻译： 一种布线板，包括：第一表面，其上设置有第一电极;第二表面，其上设置有第二电极; 至少单个绝缘层和至少一个布线层; 以及一个或多个安装的半导体元件，其中设置在第二表面上的第二电极嵌入在绝缘层中，在第二电极的第二表面侧上的暴露表面的相对侧上的表面连接到布线 层，并且第二电极的全部或部分侧面不与绝缘层接触。

公开(公告)号：US07745736B2

公开(公告)日：2010-06-29

申请号：US11341445

申请日：2006-01-30

申请人： Kenta Ogawa ,  Jun Tsukano ,  Takehiko Maeda ,  Tadanori Shimoto ,  Shintaro Yamamichi ,  Kazuhiro Baba

发明人： Kenta Ogawa ,  Jun Tsukano ,  Takehiko Maeda ,  Tadanori Shimoto ,  Shintaro Yamamichi ,  Kazuhiro Baba

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K3/205 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511 ,  H05K1/113 ,  H05K3/107 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2201/096 ,  H05K2203/0384 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interconnecting substrate is provided with a base insulating film having a sunken section in a bottom surface thereof, a first interconnection provided in the sunken section, a via hole formed in the base insulating film, and a second interconnection which is connected to the first interconnection via a conductor within the via hole and is formed on a top surface of the base insulating film, wherein the interconnecting substrate includes a first interconnection pattern formed of the first interconnection which includes at least a linear pattern which extends along a second direction orthogonal to a first direction, and a warpage-controlling pattern which is provided in the sunken section in the bottom surface of the base insulating film and is formed in such a manner as to suppress a warpage of the interconnecting substrate toward a bottom side on both sides of the first direction.

摘要翻译： 互连基板设置有在底面具有下沉部分的基底绝缘膜，设置在凹陷部分中的第一互连，形成在基底绝缘膜中的通孔，以及连接到第一互连件的第二互连 通过所述通孔内的导体，并形成在所述基底绝缘膜的顶表面上，其中所述互连衬底包括由所述第一互连形成的第一互连图案，所述第一互连图案至少包括沿着与第一互连正交的第二方向延伸的线状图案 第一方向和翘曲控制图案，其设置在基底绝缘膜的底面的下沉部分中，并且形成为抑制互连基板朝向底部绝缘膜两侧的底侧的翘曲 第一个方向

公开(公告)号：US20070079986A1

公开(公告)日：2007-04-12

申请号：US11542309

申请日：2006-10-04

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

IPC分类号： H05K1/11 ,  H05K3/30

CPC分类号： H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2203/0733 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00

摘要： A multilayered wiring board has electrodes disposed on a first surface and a second surface, alternately layered insulation layers and wiring layers, and vias that are disposed in the insulation layer and electrically connect the wiring layers. The second electrode disposed on the second surface is embedded in the insulation layer exposed on said second surface, and the second wiring layer covered by the insulation layer exposed on said second surface does not have a layer for improving adhesion to the insulation layer.

摘要翻译： 多层布线基板具有设置在第一表面和第二表面上的电极，交替层叠的绝缘层和布线层以及布置在绝缘层中并且电连接布线层的通孔。 设置在第二表面上的第二电极嵌入在暴露在所述第二表面上的绝缘层中，并且由暴露在所述第二表面上的绝缘层覆盖的第二布线层不具有用于改善与绝缘层的粘附性的层。

公开(公告)号：US06524905B2

公开(公告)日：2003-02-25

申请号：US09903316

申请日：2001-07-11

申请人： Shintaro Yamamichi ,  Toru Mori ,  Akinobu Shibuya ,  Takao Yamazaki ,  Yuzo Shimada

发明人： Shintaro Yamamichi ,  Toru Mori ,  Akinobu Shibuya ,  Takao Yamazaki ,  Yuzo Shimada

IPC分类号： H01L218242

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L27/0688 ,  H01L2221/68363 ,  H01L2224/04042 ,  H01L2224/4847 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00

摘要： A semiconductor device provided with a thin film capacitor having a small equivalent series inductance is provided, which can be operated at a high frequency range and contributes to size reduction of the electronic devices. The semiconductor device comprises a device formed on a silicon substrate 1a, interlayer insulating films 3a, 3b, and 3c, wiring blocks including a power source wire block and a ground wire block, and a thin film capacitor 14 formed on an uppermost insulating layer. The thin film capacitor 14 comprises a lower electrode 6 connected to the ground wire block 4e through a contact 5d, an upper electrode 8 which is connected to the power source wire block 4d through a contact 5d, and which extends above the lower electrode 6, and a dielectric layer 7 which is inserted between the lower and the upper electrodes.

摘要翻译： 提供了具有小等效串联电感的薄膜电容器的半导体器件，其可以在高频范围下操作并且有助于电子器件的尺寸减小。 半导体器件包括形成在硅衬底1a，层间绝缘膜3a，3b和3c上的器件，包括电源线块和接地线块的布线块，以及形成在最上层绝缘层上的薄膜电容器14。 薄膜电容器14包括通过接触件5d连接到接地线块4e的下电极6，通过接触件5d连接到电源线块4d并且在下电极6上方延伸的上电极8， 以及插入在下电极和上电极之间的电介质层7。

公开(公告)号：US06225133B1

公开(公告)日：2001-05-01

申请号：US08299407

申请日：1994-09-01

申请人： Shintaro Yamamichi ,  Hirohito Watanabe ,  Yoichi Miyasaka

发明人： Shintaro Yamamichi ,  Hirohito Watanabe ,  Yoichi Miyasaka

IPC分类号： H01L2100

CPC分类号： H01L28/55 ,  H01L27/1085 ,  Y10T29/417 ,  Y10T29/43

摘要： After an interlayer insulating film is deposited on a silicon substrate, a contact hole or contact holes is or are formed at a desired position(s) and, then, after a polysilicon layer is deposited and the contact hole(s) is (are) embedded, the surface of the polysilicon layer is flattened by chemical and mechanical polishing using at least one of piperazine or colloidal silica slurry, and a barrier metal film 4 and a highly dielectric thin film 5 are deposited and processed to a desired size. Finally, an Al/TiN film 6 adapted for the upper electrode is formed. The leak current of the thin film capacitor which is obtained according to this method can be greatly reduced.

摘要翻译： 在硅衬底上沉积层间绝缘膜之后，在期望的位置形成或形成接触孔或接触孔，然后在沉积多晶硅层并且接触孔之后， 通过使用哌嗪或胶体二氧化硅浆料中的至少一种的化学和机械抛光使多晶硅层的表面平坦化，并且将阻挡金属膜4和高电介质薄膜5沉积并加工成所需的尺寸。 最后，形成适用于上电极的Al / TiN膜6。 根据该方法获得的薄膜电容器的漏电流可以大大降低。

公开(公告)号：US5366920A

公开(公告)日：1994-11-22

申请号：US229423

申请日：1994-04-12

申请人： Shintaro Yamamichi ,  Hirohito Watanabe ,  Toshiki Hashimoto ,  Toshiyuki Sakuma

发明人： Shintaro Yamamichi ,  Hirohito Watanabe ,  Toshiki Hashimoto ,  Toshiyuki Sakuma

IPC分类号： H01G4/33 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L28/40 ,  H01L28/55

摘要： A thin film capacitor which comprises a lower electrode, a dielectric film and an upper electrode is fabricated on a substrate. The lower electrode is not provided by etching process using a photoresist mask, but it is provided by providing an aperture thorough an insulating layer deposited on the substrate, and depositing a conductive film on the bottom of the aperture and connected to a lower interconnection provided on the bottom of the aperture. Consequently, no convex protrusion is found at the processed edge of the lower electrode.

摘要翻译： 在基板上制造包括下电极，电介质膜和上电极的薄膜电容器。 下部电极不是通过使用光致抗蚀剂掩模的蚀刻工艺提供的，而是通过提供沉积在基板上的绝缘层的孔，并且在孔的底部上沉积导电膜并连接到设置在其上的下部互连 孔的底部。 因此，在下电极的处理边缘处没有发现凸起。

公开(公告)号：US08929090B2

公开(公告)日：2015-01-06

申请号：US13574455

申请日：2011-01-07

申请人： Yoshiki Nakashima ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Kentaro Mori ,  Hideya Murai

发明人： Yoshiki Nakashima ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Kentaro Mori ,  Hideya Murai

IPC分类号： H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： H05K1/182 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/18162 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/185 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T428/24322 ,  H01L2924/00

摘要： An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized. According to the present invention, there is provided a functional element built-in substrate including a functional element provided with an electrode terminal on one surface side of the functional element, and a wiring substrate including a laminated structure in which the functional element is embedded so that the electrode terminal of the functional element faces the front surface side of the structure, and which is formed at least in a side surface region of the functional element by laminating a plurality of wiring insulating layers each including a wiring, the functional element built-in substrate being featured in that the electrode terminal and the back surface side of the wiring substrate are electrically connected to each other through the wiring of the laminated structure, and in that, in a pair of the wiring insulating layers included in the laminated structure and that are in contact with each other, the cross-sectional shape of the wiring in each of the wiring insulating layers, which cross-sectional shape is taken along the plane perpendicular to the extension direction of the wiring in the wiring insulating layer, has a relationship that the cross-sectional area of the wiring in the back surface side wiring insulating layer is larger than the cross-sectional area of the wiring in the front surface side wiring insulating layer.

摘要翻译： 本发明的目的是提出一种功能元件内置基板，其使功能元件的电极端子能够良好地连接到与功能元件的电极端子相反的一侧的背面，并且其可以是 小型化。 根据本发明，提供了一种功能元件内置基板，其包括在功能元件的一个表面侧上设置有电极端子的功能元件，以及包括功能元件嵌入其中的层叠结构的布线基板 所述功能元件的电极端子面向所述结构的前表面侧，并且通过层叠多个布线绝缘层而形成在所述功能元件的至少侧面区域中，所述多个布线绝缘层包括布线， 其特征在于，布线基板的电极端子和背面侧通过层叠结构的布线电连接，并且其中，在层叠结构中包括的一对布线绝缘层和 彼此接触，每个布线绝缘中的布线的横截面形状 与布线绝缘层中的配线的延伸方向垂直的平面截取的截面形状的层具有这样的关系：背面侧配线绝缘层中的布线的截面积大于 表面侧配线绝缘层中的配线的截面积。