公开(公告)号：US07858437B2

公开(公告)日：2010-12-28

申请号：US11706186

申请日：2007-02-15

申请人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jung-Hyun Park

发明人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jung-Hyun Park

IPC分类号： H01L21/44

CPC分类号： H01L21/481 ,  H01L23/13 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1058 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K3/205 ,  H05K3/4658 ,  H05K3/4697 ,  H05K2203/0568 ,  H05K2203/0571 ,  H05K2203/308 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.

摘要翻译： 本发明的一个方面的特征在于一种用于制造具有腔的衬底的方法。 该方法可以包括：（a）在上部种子层上形成上层电路; （b）在要形成空腔的上种子层的一部分上层压干膜; （c）通过在上部种子层的顶部和上层电路的顶部和侧面上形成绝缘层来制造上部外层; （d）在形成有内部电路的芯层的一侧堆叠上外层; （e）去除上部种子层; 和（f）通过去除干膜形成空腔。 根据本发明的用于制造具有腔的衬底的方法可以通过在外部电路的侧面上形成绝缘层来减小衬底的总厚度，同时绝缘层的厚度保持相同。

公开(公告)号：US20090233400A1

公开(公告)日：2009-09-17

申请号：US12453832

申请日：2009-05-22

申请人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

发明人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC分类号： H01L21/98 ,  B32B38/10

CPC分类号： H05K3/4691 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K1/189 ,  H05K3/4623 ,  H05K2201/055 ,  H05K2201/09536 ,  H05K2201/10515 ,  H05K2203/049 ,  H05K2203/063 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A manufacturing method for rigid-flexible multi-layer printed circuit board including: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. When the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.

摘要翻译： 一种刚性柔性多层印刷电路板的制造方法，包括：柔性基板，其两侧形成有可弯曲的电路; 层叠在柔性基板上的刚性基板和电路形成在两侧，并且形成有安装半导体芯片的空腔; 以及粘合柔性基板和刚性基板并具有绝缘性的粘合片。 当安装相同数量的半导体芯片或实施POP时，封装的整体厚度可以更低。 此外，可以使用空间作为芯层的厚度来安装另外两个半导体芯片，并且可以实现当传统技术中安装在底部基板上的半导体芯片的数量变为二倍时的结构不可行。

公开(公告)号：US07494844B2

公开(公告)日：2009-02-24

申请号：US11524402

申请日：2006-09-21

申请人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

发明人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC分类号： H01L21/44

CPC分类号： H05K3/4652 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/183 ,  H05K3/205 ,  H05K3/4697 ,  H05K2201/09536 ,  H05K2203/0574 ,  H05K2203/063 ,  H05K2203/308 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

摘要： A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method in accordance with the present invention can mount a plurality of integrated circuits by reducing the thickness of a substrate on a package on package.

摘要翻译： 公开了一种用于制造具有空腔的衬底的方法。 该方法包括：（a）通过使用第一干膜在种子层的一侧上形成第一电路图案; （b）在第一干膜上层压第二干膜，第二干膜的厚度对应于待形成的空腔的深度; （c）在要形成空腔的区域外的区域上层叠电介质层，所述电介质层的厚度对应于待形成的空腔的深度; （d）在种子层上层叠具有第二电路图案的铜箔层叠主板; 和（e）通过在去除种子层之后剥离第一干膜和第二干膜来形成空腔。 根据本发明的方法可以通过减小封装上的封装上的衬底的厚度来安装多个集成电路。

公开(公告)号：US20080105458A1

公开(公告)日：2008-05-08

申请号：US11976762

申请日：2007-10-26

申请人： Myung-Sam Kang ,  Jung-Hyun Park ,  Sang-Duck Kim ,  Ji-Eun Kim ,  Jong-Gyu Choi

发明人： Myung-Sam Kang ,  Jung-Hyun Park ,  Sang-Duck Kim ,  Ji-Eun Kim ,  Jong-Gyu Choi

IPC分类号： H05K1/09 ,  H05K3/00

CPC分类号： H01L23/13 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49816 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/107 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49147 ,  H01L2224/29099 ,  H01L2924/00

摘要： A substrate for mounting a flip chip and a method of manufacturing the substrate method of manufacturing the substrate are disclosed. Using a method of manufacturing a substrate for flip chip mounting that includes providing an insulating layer, in which a circuit pattern is buried, and forming at least one bump pad shaped as an indentation by removing at least one portion of the circuit pattern, the bumps pads can be formed by removing portions of a circuit pattern in the shape of indentations, to prevent solder bumps from flowing to the insulating layer portions and reduce the pitch between bumps.

摘要翻译： 公开了一种用于安装倒装芯片的基板和制造基板的制造方法的方法。 使用制造用于倒装芯片安装的衬底的方法，其包括提供绝缘层，其中埋置电路图案，并且通过去除电路图案的至少一部分形成形成凹陷的至少一个凸块焊盘，所述凸块 可以通过去除凹陷形状的电路图案的部分来形成焊盘，以防止焊料凸块流到绝缘层部分并降低凸块之间的间距。

公开(公告)号：US20070278651A1

公开(公告)日：2007-12-06

申请号：US11708567

申请日：2007-02-21

申请人： Myung-Sam Kang

发明人： Myung-Sam Kang

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/007 ,  H05K3/20 ,  H05K3/284 ,  H05K3/4007 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2203/0361 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic component package and a manufacturing method thereof are disclosed. A method of manufacturing an electronic component package, which includes: forming a protrusion part on a first carrier board; stacking an insulation layer on the first carrier board and forming a circuit pattern, which includes a bonding pad and a solder ball pad, on the surface of the insulation layer; mounting an electronic component on the surface of the insulation layer and electrically connecting the electronic component and the bonding pad; and removing the first carrier board and the protrusion part, allows the mounting of the electronic component with just a single circuit pattern layer.

摘要翻译： 公开了一种电子部件封装及其制造方法。 一种制造电子部件封装的方法，包括：在第一载体板上形成突出部; 在第一载体板上堆叠绝缘层，并在绝缘层的表面上形成包括焊盘和焊球垫的电路图案; 将电子部件安装在所述绝缘层的表面上并电连接所述电子部件和所述焊盘; 并且移除第一载体板和突起部分允许仅使用单个电路图案层来安装电子部件。

公开(公告)号：US20070190764A1

公开(公告)日：2007-08-16

申请号：US11706186

申请日：2007-02-15

申请人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jung-Hyun Park

发明人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jung-Hyun Park

IPC分类号： H01L21/20

CPC分类号： H01L21/481 ,  H01L23/13 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1058 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K3/205 ,  H05K3/4658 ,  H05K3/4697 ,  H05K2203/0568 ,  H05K2203/0571 ,  H05K2203/308 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the-upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.

摘要翻译： 本发明的一个方面的特征在于一种用于制造具有腔的衬底的方法。 该方法可以包括：（a）在上种子层上形成上层电路; （b）在要形成空腔的上部种子层的一部分上层叠干膜; （c）通过在上部种子层的顶部和上层电路的顶部和侧面上形成绝缘层来制造上部外层; （d）在形成有内部电路的芯层的一侧堆叠上外层; （e）去除上部种子层; 和（f）通过去除干膜形成空腔。 根据本发明的用于制造具有腔的衬底的方法可以通过在外部电路的侧面上形成绝缘层来减小衬底的总厚度，同时绝缘层的厚度保持相同。

公开(公告)号：US06755229B2

公开(公告)日：2004-06-29

申请号：US09984282

申请日：2001-10-29

申请人： Myung-Sam Kang ,  Keon-Yang Park ,  Jang-Kyu Kang

发明人： Myung-Sam Kang ,  Keon-Yang Park ,  Jang-Kyu Kang

IPC分类号： B32B3500

CPC分类号： H01L21/50 ,  H01L23/36 ,  H01L23/49816 ,  H01L2924/0002 ,  Y10T156/1744 ,  H01L2924/00

摘要： Disclosed are a method for preparing a high performance BGA board and a jig applicable to the method. The method comprises pre-bonding an adhesive to a BGA board laminated structure or a heatsink by use of a jig; and main-bonding the BGA board laminated structure or the heatsink to which the adhesive is previously stuck in the pre-bonding step to the heatsink or the BGA board laminated structure, respectively, by use of a jig. A high performance BGA board can be prepared by use of an individual heatsink and a strip-type jig without a strip-type heatsink, and in which the Ni-plated side of the heatsink can be prevented from being contaminated.

摘要翻译： 公开了一种制备适用于该方法的高性能BGA板和夹具的方法。 该方法包括使用夹具将粘合剂预粘合到BGA板层叠结构或散热片上; 并且通过使用夹具将BGA板层压结构或粘合剂预先粘附在预粘合步骤中的散热器分别主要粘合到散热器或BGA板层叠结构。 可以通过使用单独的散热器和无带式散热器的带状夹具来制备高性能BGA板，并且可以防止散热器的镀镍侧被污染。

公开(公告)号：US06747450B2

公开(公告)日：2004-06-08

申请号：US10140294

申请日：2002-05-08

申请人： Myung-Sam Kang ,  Kyoung-Won Na ,  Sang-On Choi ,  Won-Youl Choi ,  Jeong-Hwan Lee ,  Keon-Yang Park

发明人： Myung-Sam Kang ,  Kyoung-Won Na ,  Sang-On Choi ,  Won-Youl Choi ,  Jeong-Hwan Lee ,  Keon-Yang Park

IPC分类号： G01R3304

CPC分类号： H05K1/165 ,  G01R33/05 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/086 ,  H05K2201/09536 ,  H05K2201/10416

摘要： A weak-magnetic field sensor using printed circuit board manufacturing technique and a method of manufacturing the same which detects earth magnetism to obtain positional information is disclosed. The sensor comprises a magnetic layer patterned in a certain shape; a first stacked board stacked on a lower surface of the magnetic layer and formed with a first driving pattern; a second stacked board stacked on an upper surface of the magnetic layer and formed with a second driving pattern, the first and second driving patterns being electrically connected to each other; a third lower stacked board stacked on a lower surface of the first stacked board and formed with a first pickup pattern; and a third upper stacked board stacked on an upper surface of the second stacked board and formed with a second pickup pattern, the third lower and upper stacked boards being electrically connected to each other.

摘要翻译： 公开了使用印刷电路板制造技术的弱磁场传感器及其制造方法，其检测地磁以获得位置信息。 传感器包括以特定形状图案化的磁性层; 堆叠在所述磁性层的下表面上并形成有第一驱动图案的第一堆叠板; 堆叠在所述磁性层的上表面上并形成有第二驱动图案的第二堆叠板，所述第一和第二驱动图案彼此电连接; 堆叠在第一堆叠板的下表面上并形成有第一拾取图案的第三下堆叠板; 以及堆叠在所述第二堆叠板的上表面上并形成有第二拾取图案的第三上堆叠板，所述第三下堆叠板和上堆叠板彼此电连接。

公开(公告)号：US08633392B2

公开(公告)日：2014-01-21

申请号：US13354438

申请日：2012-01-20

申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC分类号： H05K1/02

CPC分类号： H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

摘要： A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.

摘要翻译： 一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。

公开(公告)号：US20110259627A1

公开(公告)日：2011-10-27

申请号：US13067883

申请日：2011-07-01

申请人： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

发明人： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC分类号： H05K1/09 ,  H05K1/11

CPC分类号： H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator.

摘要翻译： 电路板包括：具有凹槽的绝缘体; 填充所述凹槽的一部分的电路层; 电路层上的填充凹槽其余部分的焊盘; 以及与电路层电连接的电路图案，电路图案埋在绝缘体中，使得电路图案的一部分在绝缘体的表面露出。