公开(公告)号：US20010023532A1

公开(公告)日：2001-09-27

申请号：US09799684

申请日：2001-03-07

发明人： Hirofumi Fujii ,  Satoshi Tanigawa

IPC分类号： H05K003/36 ,  B23P017/00

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L23/3107 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/007 ,  H05K3/108 ,  H05K3/20 ,  H05K3/388 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4644 ,  H05K3/4652 ,  H05K3/4658 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2203/0152 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4981 ,  H01L2924/00

摘要： A producing method of a multilayer circuit board for ensuring that a circuit board, such as an interposer, is provided on the multilayer circuit board. The method includes the steps of forming the interposer on a support board; forming a multilayer circuit board separately from the interposer; joining the interposer formed on the support board to the multilayer circuit board; and then removing the support board. According to this method, even if the production of the interposer fails after the production of the multilayer circuit board, it is possible to scrape the interposer only and there is no need to scrap it together with the multilayer circuit board. Besides, although the interposer is so thin and limp, since it is formed on the support board, the interposer can surely and readily be joined to the multilayer circuit board.

摘要翻译： 一种多层电路板的制造方法，用于确保在多层电路板上设置诸如插入件的电路板。 该方法包括在支撑板上形成插入件的步骤; 与所述插入件分开形成多层电路板; 将形成在所述支撑板上的所述插入件接合到所述多层电路板; 然后卸下支撑板。 根据该方法，即使在制造多层电路板之后插入件的制造失败，也可以仅刮擦插入件，并且不需要与多层电路板一起将其废弃。 此外，虽然内插器如此薄且跛行，但是由于其形成在支撑板上，所以插入件可以可靠地容易地接合到多层电路板。

公开(公告)号：US20010018797A1

公开(公告)日：2001-09-06

申请号：US09773049

申请日：2001-01-31

发明人： Paul N. Shepherd

IPC分类号： H05K003/36 ,  H05K003/02

CPC分类号： H01L23/5383 ,  H01L21/4857 ,  H01L21/4867 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4629 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： A low temperature co-fired ceramic assembly (LTCC) with a constraining core to minimize shrinkage of outer ceramic layers during firing. The outer ceramic layers have high density circuit features. A ceramic core includes several ceramic layers. Several via holes are located in the first and second ceramic layers. Several low density circuit features are located on the ceramic layers that make up the core. Outer ceramic layers are placed top and bottom of the ceramic core. The outer ceramic layers have via holes and high density circuit features. The circuit features patterned on the ceramic layers include resistors, capacitors, circuit lines, vias, inductors, or bond pads. The ceramic core is fired first in a furnace. The outer layers are then laminated to the ceramic core and fired. The ceramic core controls the shrinkage rate of the outer ceramic layers during firing allowing higher density circuit features on the outer layers.

公开(公告)号：US20010011605A1

公开(公告)日：2001-08-09

申请号：US09779117

申请日：2001-02-08

发明人： Thomas H. Distefano ,  Joseph Fjelstad

IPC分类号： H05K003/36 ,  C09J001/00 ,  B65H029/00 ,  B32B031/00

CPC分类号： H05K3/462 ,  H01L23/49827 ,  H01L23/5385 ,  H01L2924/0002 ,  H01R12/523 ,  H01R12/714 ,  H01R13/2414 ,  H01R43/0256 ,  H05K1/0272 ,  H05K1/036 ,  H05K1/056 ,  H05K1/116 ,  H05K3/0032 ,  H05K3/326 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1744 ,  H01L2924/00

摘要： An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact extends from a central conductor, and has a peripheral portion adapted to contract radially inwardly toward the central conductor response to a force applied by a contact pad defining a central hole on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts contract radially inwardly and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.

摘要翻译： 用于微电子电路板之间的互连的插入件在其表面具有接触。 每个接触件从中心导体延伸，并且具有适于从中心导体径向向内收缩的外围部分，以响应由在所接合的电路板上限定中心孔的接触垫施加的力。 因此，当电路板被内插件压缩时，触头径向向内收缩并且擦拭穿过焊盘。 擦拭动作有助于通过摩擦焊接将接触件接合到焊盘，或者通过接触件本身承载的导电接合材料。

公开(公告)号：US20040216838A1

公开(公告)日：2004-11-04

申请号：US10478546

申请日：2003-11-21

发明人： Anders V. Ekman ,  Richard Stossel ,  Thierry Becret ,  Thierry Tschan ,  Kurt Stutz

IPC分类号： H05K003/36 ,  H05K003/46

CPC分类号： H05K3/4655 ,  H05K3/4652 ,  H05K2203/0759 ,  Y10T29/49126

摘要： Method for the production of components for electronic apparatuses from a sheet-like substrate material, which has through-holes and indentations on at least one surface, an intermediate layer on at least one surface of the substrate material, and a metal foil adhering to said layer, comprising the steps (a) coating of a sheet-like substrate with a composition forming the intermediate layer, (b) application of the metal foil to the coating and (c) bonding of the parts by pressure and heating. The method is characterized by the use of a liquid, solvent-containing and heat-curable two-component system comprising at least one curing agent and at least one curable compound, which system is applied as the layer to at least one surface of a substrate material and then dried. A metal foil is then laminated with the resulting solid and dry layer under pressure and at elevated temperature and the layer is cured. Particularly preferably, circuit boards are produced by the method according to the invention.

摘要翻译： 用于从片状基片材料生产电子设备用部件的方法，所述片状基片材料在至少一个表面上具有通孔和凹陷，所述基底材料的至少一个表面上的中间层和附着在所述基底材料上的金属箔 层，包括步骤（a）用形成中间层的组合物涂覆片状基材，（b）将金属箔施加到涂层上，和（c）通过压力和加热粘合部件。 该方法的特征在于使用包含至少一种固化剂和至少一种可固化化合物的液体，含溶剂和可热固化的双组分体系，该系统作为该层被施加到基底的至少一个表面 材料然后干燥。 然后将金属箔与所得的固体和干燥层在压力和升高的温度下层压，并且该层被固化。 特别优选的是，通过根据本发明的方法制造电路板。

公开(公告)号：US20040194299A1

公开(公告)日：2004-10-07

申请号：US10823437

申请日：2004-04-12

申请人： FormFactor, Inc.

发明人： Gary W. Grube ,  Igor Y. Khandros ,  Benjamin N. Eldridge ,  Gaetan L. Mathieu

IPC分类号： H05K003/36 ,  B21K001/42 ,  G05F001/00

CPC分类号： G01R1/07314 ,  G01R1/07342 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2886 ,  G01R31/2889 ,  Y10T29/49002 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49453

摘要： A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

公开(公告)号：US20040187304A1

公开(公告)日：2004-09-30

申请号：US10741824

申请日：2003-12-19

申请人： APPLIED MATERIALS, INC.

发明人： Ling Chen ,  Mei Chang

IPC分类号： H05K003/00 ,  H05K003/36

CPC分类号： H01L21/76849 ,  C23C16/34 ,  C23C16/45525 ,  H01L21/28562 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155

摘要： A method for depositing a cap layer over a metal-containing interconnect is provided. In one aspect, the cap layer is formed by introducing a pulse of a metal-containing compound followed by a pulse of a nitrogen-containing compound. In one aspect, the cap layer comprises tantalum nitride. The cap layer provides good barrier and adhesive properties, thereby enhancing the electrical performance and reliability of the interconnect.

摘要翻译： 提供了一种用于在含金属互连上沉积覆盖层的方法。 在一个方面，通过引入含金属化合物的脉冲，接着是含氮化合物的脉冲来形成盖层。 在一个方面，盖层包括氮化钽。 盖层提供良好的阻隔性和粘合性，从而增强互连的电性能和可靠性。

公开(公告)号：US20040139603A1

公开(公告)日：2004-07-22

申请号：US10755983

申请日：2004-01-13

申请人： NEC Electronics Corporation ,  NEC Corporation

发明人： Nobuaki Takahashi ,  Yuji Akimoto ,  Mikio Oda ,  Hikaru Kouta

IPC分类号： H05K003/36 ,  H01R009/00

CPC分类号： H01L21/6835 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H05K1/092 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0113 ,  H05K2203/0338 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05644

摘要： Disclosed is a wired board with a bump electrode whose production efficiency is improved. A high-concentration impurity Si template doped with boron and having a pit formed therein is prepared. A plated resist is formed on the high-concentration impurity Si template and an opening is formed in portion for the pit. Then, an electric field is applied to the high-concentration impurity Si template and Au is buried in the opening in the plated resist to form an Au-plated buried layer. An electrode pad is formed on a semiconductor chip. With the plated resist separated from the high-concentration impurity Si template, the electrode pad of the semiconductor chip is aligned with the Au-plated buried layer and is bonded by thermo-compression bonding. The Au-plated buried layer is transferred to the electrode pad to form Au bump on the semiconductor chip.

摘要翻译： 公开了一种具有凸起电极的布线板，其生产效率得到改善。 制备掺杂有硼并在其中形成凹坑的高浓度杂质Si模板。 在高浓度杂质Si模板上形成电镀抗蚀剂，并且为凹坑形成一部分开口。 然后，对高浓度杂质Si模板施加电场，将Au埋入镀敷抗蚀剂的开口部，形成镀Au埋层。 在半导体芯片上形成电极焊盘。 通过将电镀抗蚀剂与高浓度杂质Si模板分离，将半导体芯片的电极焊盘与镀Au掩埋层对准，并通过热压接而结合。 将镀Au掩埋层转移到电极焊盘，以在半导体芯片上形成Au凸块。

公开(公告)号：US20040100772A1

公开(公告)日：2004-05-27

申请号：US10323150

申请日：2002-12-18

发明人： Lim Thiam Chye ,  Setho Sing Fee ,  Eric Tan Swee Seng

IPC分类号： G06F001/16 ,  H05K007/00 ,  H05K007/04 ,  H05K003/36

CPC分类号： H01L25/105 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  Y10T29/49126 ,  Y10T29/49208 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00

摘要： Various aspects of the invention provide microelectronic component assemblies, memory modules, computer systems, and methods of assembling microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a non-leaded first package, a second package, and a plurality of electrical junctions. The first package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces. The second package has a confronting surface that includes an exposed back surface of a microelectronic component and exposed contact surfaces of a number of leads. Each of the junctions couples one of the contacts to the contact surface of one of the leads. The electrical junctions may also physically support the packages with their respective confronting surfaces juxtaposed with but spaced from one another, defining a peripherally open fluid passage and enhancing thermal performance.

摘要翻译： 本发明的各个方面提供微电子部件组件，存储器模块，计算机系统以及组装微电子部件组件的方法。 在一个具体实现中，微电子部件组件包括非引线第一封装，第二封装和多个电连接。 第一包装具有面对的表面，其包括微电子部件的暴露后表面和暴露的接触表面。 第二包装具有面对的表面，其包括微电子部件的暴露后表面和多个引线的暴露的接触表面。 每个连接点将触点中的一个耦合到其中一个引线的接触表面。 电接头还可以物理地支撑包装件，其各自的相对表面彼此并置但间隔开，限定了外围开放的流体通道并增强热性能。

公开(公告)号：US20040089472A1

公开(公告)日：2004-05-13

申请号：US10354972

申请日：2003-01-31

申请人： TDK CORPORATION

发明人： Hideaki Ninomiya ,  Haruo Nishino ,  Kiyoshi Hatanaka

IPC分类号： H05K003/36 ,  H05K003/02 ,  H05K001/03 ,  H05K001/11

CPC分类号： H01L23/15 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/183 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4697 ,  H05K2203/063 ,  Y10T29/43 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49833 ,  Y10T428/252 ,  H01L2924/00

摘要： This invention provides a multilayer ceramic substrate which has a consistent quality, and which has with no swelling or collapse in the inner periphery of the cavity, wherein the bottom of the cavity is flat to enable stable packaging of the desired device at a high precision, and wherein L and C can be formed by the internal conductor at a high precision; and a method for producing a multilayer ceramic substrate and an apparatus therefor by which a multilayer ceramic substrate can be readily produced in a simple procedure by using an apparatus of simple structure. This invention has realized a multilayer ceramic substrate comprising a laminate constituted from laminated ceramic layers 1a to 1h and internal conductors 3 formed between the ceramic layers 1a to 1h, wherein the laminate has end surfaces on opposite ends of its thickness direction, and the laminate is formed with a cavity 2 which opens to at least one end surface of the laminate, and wherein the multilayer ceramic substrate is provided at least with a capacitor and/or an inductor constituted by the internal conductors 3; its production method; and an apparatus used in such production.

摘要翻译： 本发明提供了一种多层陶瓷基板，其具有一致的质量，并且在空腔的内周边没有膨胀或塌陷，其中空腔的底部是平坦的，以能够以高精度稳定地包装所需的装置， 并且其中L和C可以由内部导体以高精度形成; 以及一种制造多层陶瓷基板的方法及其装置，通过使用简单结构的装置，可以通过简单的程序容易地制造多层陶瓷基板。 本发明实现了一种多层陶瓷基板，其包括由层叠陶瓷层1a至1h构成的层压体和形成在陶瓷层1a至1h之间的内部导体3，其中层压体具有其厚度方向的相对端上的端面，层压体为 形成有通向所述层叠体的至少一个端面的空腔2，并且其中所述多层陶瓷基板至少设置有由所述内部导体3构成的电容器和/或电感器; 其生产方式; 以及在这种生产中使用的装置。

公开(公告)号：US20040085000A1

公开(公告)日：2004-05-06

申请号：US10694513

申请日：2003-10-27

申请人： Murata Manufacturing Co., Ltd.

发明人： Mitsugu Ogiura

IPC分类号： H04R017/00 ,  H01L041/04 ,  H05K003/36

CPC分类号： G01P15/0922 ,  Y10T29/42 ,  Y10T29/49004 ,  Y10T29/49005 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49789 ,  Y10T29/49798

摘要： An acceleration sensor includes a piezoelectric element and support frames for supporting the ends of the piezoelectric element in the longitudinal direction. The piezoelectric element is formed by stacking an even number of piezoelectric layers greater than or equal to four layers. Electrodes are provided in between the layers and on the front and back faces of the piezoelectric element. The interlayer electrodes including a segmented electrode and lead electrodes are alternately stacked with the piezoelectric layers therebetween. The interlayer electrode in the middle in the thickness direction is a segmented electrode. The piezoelectric layers are polarized in the thickness direction so that charge having the same polarity is extracted from the electrodes when the acceleration is applied. Also, the center portion and both end portions of each piezoelectric layer are polarized in opposite directions.

摘要翻译： 加速度传感器包括压电元件和用于在纵向方向上支撑压电元件的端部的支撑框架。 压电元件通过层叠大于或等于四层的偶数个压电层而形成。 电极设置在层之间以及压电元件的正面和背面上。 包括分段电极和引线电极的层间电极与它们之间的压电层交替堆叠。 厚度方向中间的层间电极是分段电极。 压电层在厚度方向上极化，使得当施加加速度时，从电极中提取具有相同极性的电荷。 此外，每个压电层的中心部分和两个端部部分在相反的方向上极化。