公开(公告)号：US07826551B2

公开(公告)日：2010-11-02

申请号：US11501786

申请日：2006-08-10

Applicant: Hee-Seok Lee ,  Sung-hwan Min

Inventor： Hee-Seok Lee ,  Sung-hwan Min

IPC: H04B3/46 ,  H04B17/00 ,  H04Q1/20

CPC classification number: H04L25/0272

Abstract: In one aspect, a differential signal transfer method is provided which includes converting 2M−1 original signals into 2M−1 differential signal pairs, where M is an integer of 2 or more, and wherein each pair consists of a first differential signal and a second differential signal having opposite phases, and transferring the 2M−1 differential signal pairs to 2M signal lines such that each of the 2M signal lines includes overlapping differential signals among the first differential signals and the second differential signals of the 2M−1 differential signal pairs.

Abstract translation: 一方面，提供了一种差分信号传送方法，其包括将2M-1个原始信号转换为2M-1个差分信号对，其中M是2或更大的整数，并且其中每对包括第一差分信号和第二差分信号 具有相反相位的差分信号，并将2M-1个差分信号对传送到2M信号线，使得每个2M信号线包括第一差分信号和2M-1差分信号对的第二差分信号之间的重叠差分信号。

公开(公告)号：US07768103B2

公开(公告)日：2010-08-03

申请号：US11482139

申请日：2006-07-07

Applicant: Young-sang Cho ,  Hee-seok Lee

Inventor： Young-sang Cho ,  Hee-seok Lee

IPC: H01L23/495

CPC classification number: H05K1/0216 ,  G02F1/13452 ,  H05K1/118 ,  H05K2201/09236 ,  H05K2201/0969 ,  H05K2201/09781

Abstract: A tape distribution substrate comprises a plurality of distribution lines formed on a base film. In one embodiment, the distribution lines comprise data lines arranged in data line pairs, wherein each data line pair carries a data signal with two different polarities. The distance between the data lines in each data line pair becomes narrower as the data lines extend away from the base film. In another embodiment, the distribution lines comprise power distribution lines, each having a body portion including several holes, and divided into one or more sub-power distribution lines connected to the base film.

Abstract translation: 胶带分配衬底包括形成在基膜上的多个配线。 在一个实施例中，分配线包括以数据线对布置的数据线，其中每个数据线对承载具有两个不同极性的数据信号。 随着数据线远离基膜，每条数据线对中的数据线之间的距离变窄。 在另一个实施例中，分配线包括功率分配线，每个配电线具有包括多个孔的主体部分，并且被分成连接到基膜的一个或多个子配电线。

公开(公告)号：US20100117451A1

公开(公告)日：2010-05-13

申请号：US12654991

申请日：2010-01-12

Applicant: Kyung-Lae Jang ,  Hee-Seok Lee

Inventor： Kyung-Lae Jang ,  Hee-Seok Lee

IPC: H02J4/00 ,  H01L21/60

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10T307/406 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.

公开(公告)号：US07566954B2

公开(公告)日：2009-07-28

申请号：US11084529

申请日：2005-03-18

Applicant: Kyung Lae Jang ,  Hee Seok Lee ,  Heung Kyu Kwon

Inventor： Kyung Lae Jang ,  Hee Seok Lee ,  Heung Kyu Kwon

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06179 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2224/48824 ,  H01L2924/00012

Abstract: In a bonding configuration for a semiconductor device package, the bonding angles of the bonding wires are maintained within acceptable limits, without causing an increase in the chip die size, and without necessitating the use of the corner rule. In this manner, the occurrence of shorting between adjacent bonding wires can be mitigated or eliminated, and device net die count during fabrication can be increased.

Abstract translation: 在半导体器件封装的接合构造中，接合线的接合角度保持在可接受的极限内，而不会引起芯片尺寸的增加，并且不需要使用拐角规则。 以这种方式，可以减轻或消除相邻接合线之间的短路的发生，并且可以增加制造期间的器件网芯数。

公开(公告)号：US07374969B2

公开(公告)日：2008-05-20

申请号：US11259707

申请日：2005-10-25

Applicant: Byeong-Yeon Cho ,  Hee-Seok Lee ,  Kyung-Lae Jang

Inventor： Byeong-Yeon Cho ,  Hee-Seok Lee ,  Kyung-Lae Jang

IPC: H01L21/00 ,  H01L23/02

CPC classification number: H01L24/85 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/85913 ,  H01L2224/8592 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/06 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: The present invention relates to a semiconductor package having a conductive molding compound to prevent static charge accumulation. By using a conductive molding compound heat conductivity is also increased and heat generated by the semiconductor chip is more effectively dissipated externally. Additionally, the conductive compound blocks electromagnetic waves making possible an optimal semiconductor package satisfying the electromagnetic compatibility (EMC) and increasing the reliability of the semiconductor chip especially when processing high-speed signals.

Abstract translation: 本发明涉及一种具有导电性成型化合物以防止静电积聚的半导体封装。 通过使用导电模塑料，导热性也增加，并且由半导体芯片产生的热量更有效地从外部消散。 此外，导电化合物阻止电磁波，使得能够实现满足电磁兼容性（EMC）的最佳半导体封装，并且特别是在处理高速信号时增加半导体芯片的可靠性。

公开(公告)号：US07372148B2

公开(公告)日：2008-05-13

申请号：US11274588

申请日：2005-11-14

Applicant: Yun-Hyeok Im ,  Jae-Wook Yoo ,  Hee-Seok Lee

Inventor： Yun-Hyeok Im ,  Jae-Wook Yoo ,  Hee-Seok Lee

IPC: H01L23/34

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L23/473 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a semiconductor chip coolant path, a semiconductor package utilizing the semiconductor chip coolant path, and a cooling system for the semiconductor package. For effective dissipation of heat generated during semiconductor chip operation, a semiconductor chip having a coolant path formed through or adjacent to its backside and a semiconductor package utilizing the semiconductor chip are provided. In addition, a cooling system for the semiconductor package circulates a coolant through the coolant path within the semiconductor package to directly contact and cool the semiconductor chip.

Abstract translation: 本发明涉及半导体芯片冷却剂路径，利用半导体芯片冷却剂路径的半导体封装以及半导体封装的冷却系统。 为了有效消散在半导体芯片操作期间产生的热量，提供了具有形成在其背面或靠近其背面的冷却剂通道的半导体芯片以及利用半导体芯片的半导体封装。 此外，用于半导体封装的冷却系统使冷却剂循环通过半导体封装内的冷却剂路径，以直接接触和冷却半导体芯片。

公开(公告)号：US07372139B2

公开(公告)日：2008-05-13

申请号：US11108794

申请日：2005-04-19

Applicant: Hee-seok Lee ,  Kyung-lae Jang

Inventor： Hee-seok Lee ,  Kyung-lae Jang

IPC: H01L23/52

CPC classification number: H05K3/222 ,  H01L23/49805 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/10492 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract translation: 半导体芯片封装可以包括可以在其上形成有焊盘的衬底。 安装在基板上的半导体芯片可以具有芯片焊盘和用于将半导体芯片的芯片焊盘连接到衬底焊盘的电连接。 半导体芯片和基板上的电连接可以被封装，并且附接到基板表面的一部分的板可以不被封装。

公开(公告)号：US20060157826A1

公开(公告)日：2006-07-20

申请号：US11247307

申请日：2005-10-12

Applicant: Hee-seok Lee ,  Un-byoung Kang ,  Yun-hyeok Im

Inventor： Hee-seok Lee ,  Un-byoung Kang ,  Yun-hyeok Im

IPC: H01L23/58

CPC classification number: H05K3/4641 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/09 ,  H05K2201/0338 ,  H05K2201/0352 ,  H01L2924/00

Abstract: A multi-path printed circuit board (PCB) comprising separate direct current (DC) and alternating current (AC) paths, and a power delivery system including the same are provided. The multi-path PCB comprises a plurality of planar layers, each comprising a metal layer, and a plurality of insulators interposed between the planar layers. The metal layers may have different conductivities. The power delivery system includes a power source, a semiconductor IC, and the multi-path PCB. The multi-path PCB is adapted to function as a power delivery path for delivering power from the power source to the semiconductor IC.

Abstract translation: 提供了包括单独的直流（DC）和交流（AC）路径的多路径印刷电路板（PCB），以及包括其的电力输送系统。 多路径PCB包括多个平面层，每个平面层包括金属层，以及介于平面层之间的多个绝缘体。 金属层可以具有不同的电导率。 电力输送系统包括电源，半导体IC和多路PCB。 多路径PCB适于用作将功率从电源传送到半导体IC的功率传递路径。

公开(公告)号：US20060119448A1

公开(公告)日：2006-06-08

申请号：US11296769

申请日：2005-12-06

Applicant: Hee-Seok Lee ,  Kyung-Lae Jang ,  Tae-Je Cho ,  Ki-Won Choi

Inventor： Hee-Seok Lee ,  Kyung-Lae Jang ,  Tae-Je Cho ,  Ki-Won Choi

IPC: H01P3/08

CPC classification number: H01P3/003 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/4917 ,  H01L2224/49175 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/3025 ,  H01P3/08 ,  H05K1/0219 ,  H05K3/222 ,  H05K2201/09236 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/00013

Abstract: A printed circuit board for a high-speed semiconductor package uses bonding wires as a shield structure, e.g., to shield an open portion of signal transmission lines, and thereby reduce the likelihood of coupling noises, e.g., between signal transmission lines.

Abstract translation: 用于高速半导体封装的印刷电路板使用接合线作为屏蔽结构，例如屏蔽信号传输线的开放部分，从而降低例如信号传输线之间耦合噪声的可能性。

公开(公告)号：US08872319B2

公开(公告)日：2014-10-28

申请号：US13243704

申请日：2011-09-23

Applicant: Yong-Hoon Kim ,  Hee-Seok Lee ,  Seong-Ho Shin ,  Se-Ho You ,  Yun-Hee Lee

Inventor： Yong-Hoon Kim ,  Hee-Seok Lee ,  Seong-Ho Shin ,  Se-Ho You ,  Yun-Hee Lee

IPC: H01L23/02 ,  H01L23/552 ,  H01L25/10 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.

Abstract translation: 提供堆叠的包装结构。 堆叠封装结构包括：堆叠封装，包括下半导体封装，设置在下半导体封装上并与下半导体封装隔开预定距离的上半导体封装;电连接下半导体封装和 上部半导体封装，同时支撑它们之间的空间，以及绝缘层，其至少设置在所述封装间连接部分的外部并填充所述下部半导体封装和所述上部半导体封装之间的空间，以及围绕所述下部半导体封装的横向和顶部表面的电磁屏蔽层 堆叠包装。