公开(公告)号：US20130307143A1

公开(公告)日：2013-11-21

申请号：US13539229

申请日：2012-06-29

Applicant: Jing-Cheng LIN ,  Jui-Pin HUNG

Inventor： Jing-Cheng LIN ,  Jui-Pin HUNG

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L24/10 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/82001 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.

Abstract translation: 上述晶片级封装（WLP）的机理的实施例利用平坦化停止层来确定形成再分配线（RDL）之前除去过量模塑料的终点。 WLP的这种机制被用于实现扇出和多芯片封装。 这些机构还可用于制造包括具有不同类型的外部连接的芯片（或模具）的包装。 例如，具有预先形成的凸块的模具可以与模具封装而没有预先形成的凸块。

公开(公告)号：US08569086B2

公开(公告)日：2013-10-29

申请号：US13216825

申请日：2011-08-24

Applicant: Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/00

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

Abstract translation: 提供了一种用于将基底分离成单个模具的方法和装置，并且提供了所得到的结构。 在衬底内形成诸如非晶层的改性层。 可以使用聚焦在衬底内的激光来产生修饰层。 改性层产生比周围的基材更容易破裂的相对较弱的区域。 结果，衬底可以被拉开到分开的部分中，从而沿着修饰层裂开衬底。 在分离之前或之后，骰子或其它组分可附着于基底。

公开(公告)号：US20130270690A1

公开(公告)日：2013-10-17

申请号：US13445734

申请日：2012-04-12

Applicant: Cheng-Chieh Hsieh ,  Jing-Cheng Lin

Inventor： Cheng-Chieh Hsieh ,  Jing-Cheng Lin

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L23/473 ,  H01L21/4882 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink. The integrated heat spreader is bonded to the heat sink through the bonding of the first oxide layer to the second oxide layer.

Abstract translation: 一种方法包括在集成散热器的表面上形成第一氧化物层，并且在翅片的顶表面上形成第二氧化物层，其中散热片是散热片的一部分。 集成散热器通过第一氧化物层与第二氧化物层的结合而结合到散热器。

公开(公告)号：US08557684B2

公开(公告)日：2013-10-15

申请号：US13215959

申请日：2011-08-23

Applicant: Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/301

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench.

Abstract translation: 一种方法包括执行激光切槽以去除晶片中的电介质材料以形成沟槽，其中沟槽从晶片的顶表面延伸以在晶片的顶表面和底表面之间的中间水平处停止。 沟槽在晶片中的两个相邻芯片之间的划线中。 将聚合物填充到沟槽中，然后固化。 在固化聚合物的步骤之后，执行模锯以分离两个相邻的芯片，其中模具的切口线切割填充在沟槽中的聚合物的一部分。

公开(公告)号：US20130200529A1

公开(公告)日：2013-08-08

申请号：US13369126

申请日：2012-02-08

Applicant: Jing-Cheng Lin ,  Szu Wei Lu ,  I-Hsuan Peng

Inventor： Jing-Cheng Lin ,  Szu Wei Lu ,  I-Hsuan Peng

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/18 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

Abstract: Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies.

Abstract translation: 公开了半导体器件封装方法及其结构。 在一个实施例中，封装半导体器件的方法包括将多个第二管芯耦合到第一管芯的顶表面，以及确定多个第二管芯和第一管芯之间的距离。 该方法还包括基于确定的距离来确定在第一模具和第一模具中的每一个之间配置的底部填充材料的量，以及将确定量的底部填充材料设置在多个第二模具的每一个下。

公开(公告)号：US20130193593A1

公开(公告)日：2013-08-01

申请号：US13362913

申请日：2012-01-31

Applicant: Jing-Cheng LIN ,  Cheng-Lin HUANG

Inventor： Jing-Cheng LIN ,  Cheng-Lin HUANG

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L24/16 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014

Abstract: The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.

Abstract translation: 用于形成凸块结构的机构能够在芯片和基板之间形成凸块结构，消除或降低焊料短路，焊剂残留物和底部填充物中的空隙的风险。 可以通过将结合的凸块结构中的铜柱的总高度除以接合的凸块结构的间距来限定的cc比率来限定下限，以避免短路。 也可以建立一个下限以排除芯片封装以避免焊剂残留和底部填充空隙形成。 此外，由于制造工艺限制，铜柱凸起的纵横比具有下限以避免不足的间隙和更高的极限。 通过遵循适当的凸块设计和工艺指南，芯片封装的产量和可靠性可能会增加。

公开(公告)号：US20130175694A1

公开(公告)日：2013-07-11

申请号：US13345485

申请日：2012-01-06

Applicant: Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L21/58 ,  H01L23/485 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/83

Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Abstract translation: 一种方法包括在衬底上形成电介质层，在电介质层上形成互连结构，以及将管芯结合到互连结构。 然后去除衬底，并对电介质层进行图案化。 连接器形成在电介质层的表面，其中连接器电耦合到管芯。

公开(公告)号：US20130154062A1

公开(公告)日：2013-06-20

申请号：US13328746

申请日：2011-12-16

Applicant: Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

Inventor： Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate.

Abstract translation: 提供具有沿侧壁的凸缘的模具和形成模具的方法。 还提供了一种包装模具的方法。 通过形成具有第一宽度的第一凹口，然后在第一凹口内形成第二凹槽，使得第二凹槽具有小于第一宽度的第二宽度，来切割诸如经处理晶片的基底。 第二凹口延伸穿过衬底，从而切割衬底。 第一宽度和第二宽度之间的宽度差导致沿着骰子的侧壁的凸缘。 骰子可以放置在基底上，例如插入物，以及放置在骰子和基底之间的底部填充物。 凸缘防止或减少底部填充物在相邻骰子之间的距离。 可以在基材上形成模塑料。

公开(公告)号：US08455321B2

公开(公告)日：2013-06-04

申请号：US13294526

申请日：2011-11-11

Applicant: Li-Shyue Lai ,  Jing-Cheng Lin

Inventor： Li-Shyue Lai ,  Jing-Cheng Lin

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

Abstract translation: 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

公开(公告)号：US20130122659A1

公开(公告)日：2013-05-16

申请号：US13296922

申请日：2011-11-15

Applicant: Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/56

CPC classification number: H01L24/97 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method comprises attaching a first side of an interposer on a carrier wafer. The first side of the interposer comprises a plurality of bumps. The carrier wafer comprises a plurality of cavities formed in the carrier wafer. Each bump on the first side of the interposer can fit into its corresponding cavity on the carrier wafer. Subsequently, the method comprises attaching a semiconductor die on the second side of the interposer to form a wafer stack, detaching the wafer stack from the carrier wafer and attaching the wafer stack to a substrate.

Abstract translation: 一种方法包括将插入件的第一侧附着在载体晶片上。 插入器的第一侧包括多个凸块。 载体晶片包括形成在载体晶片中的多个空腔。 插入器的第一侧上的每个凸块可以装配到载体晶片上的相应空腔中。 随后，该方法包括在插入器的第二侧上附加半导体管芯以形成晶片堆叠，将晶片堆叠与载体晶片分离并将晶片堆叠连接到基板。