公开(公告)号：US20140061888A1

公开(公告)日：2014-03-06

申请号：US13597868

申请日：2012-08-29

申请人： Jing-Cheng LIN ,  Chin-Chuan CHANG ,  Jui-Pin HUNG

发明人： Jing-Cheng LIN ,  Chin-Chuan CHANG ,  Jui-Pin HUNG

IPC分类号： H01L23/02 ,  H01L21/50

CPC分类号： H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

摘要： The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.

摘要翻译： 上述形成半导体器件封装的机构由于相对简单的工艺流程而提供了低成本的制造工艺。 通过形成具有再分布层的互连结构以使得能够在封装结构下方的一个或多个管芯接合，整体封装的翘曲大大降低。 此外，形成互连结构，而不使用模塑料，这减少了颗粒污染。 翘曲和颗粒污染的减少会提高产量。 此外，形成的半导体器件封装具有低的形状因数，其中一个或多个管芯装配在封装结构和互连结构之间的空间的下方。

公开(公告)号：US20130307143A1

公开(公告)日：2013-11-21

申请号：US13539229

申请日：2012-06-29

申请人： Jing-Cheng LIN ,  Jui-Pin HUNG

发明人： Jing-Cheng LIN ,  Jui-Pin HUNG

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L24/10 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/82001 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

摘要： The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.

摘要翻译： 上述晶片级封装（WLP）的机理的实施例利用平坦化停止层来确定形成再分配线（RDL）之前除去过量模塑料的终点。 WLP的这种机制被用于实现扇出和多芯片封装。 这些机构还可用于制造包括具有不同类型的外部连接的芯片（或模具）的包装。 例如，具有预先形成的凸块的模具可以与模具封装而没有预先形成的凸块。

公开(公告)号：US20130244378A1

公开(公告)日：2013-09-19

申请号：US13418868

申请日：2012-03-13

申请人： Chin-Fu KAO ,  Jing-Cheng LIN ,  Jui-Pin HUNG ,  Szu Wei LU

发明人： Chin-Fu KAO ,  Jing-Cheng LIN ,  Jui-Pin HUNG ,  Szu Wei LU

IPC分类号： H01L21/50

CPC分类号： H01L21/563 ,  H01L21/568 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die.

摘要翻译： 一种方法包括将载体粘合在顶模上。 该方法还包括固化设置在基底和顶模之间的底部填充物。 该方法还包括在固化期间在载体上施加力。 该方法还包括从顶模移除载体。

公开(公告)号：US20130168848A1

公开(公告)日：2013-07-04

申请号：US13338820

申请日：2011-12-28

申请人： Jing-Cheng LIN ,  Jui-Pin HUNG ,  Nai-Wei LIU ,  Yi-Chao MAO ,  Wan-Ting SHIH ,  Tsan-Hua TUNG

发明人： Jing-Cheng LIN ,  Jui-Pin HUNG ,  Nai-Wei LIU ,  Yi-Chao MAO ,  Wan-Ting SHIH ,  Tsan-Hua TUNG

IPC分类号： H01L23/498 ,  H01L21/60 ,  H01L23/48

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

摘要： The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.

摘要翻译： 提供了在半导体器件基板上形成模制化合物以使得晶片级封装（WLP）中的扇出结构能够实现的机制。 这些机构涉及覆盖围绕接触垫的绝缘层的表面的部分。 这些机制提高了包装的可靠性和包装过程的过程控制。 这些机理还降低了界面分层的风险，并且在后续处理过程中绝缘层过度消除气泡。 这些机制进一步改善了平面化终点。 通过利用接触焊盘和绝缘层之间的保护层，可以减少铜外扩散，并且还可以提高接触焊盘和绝缘层之间的粘附。

公开(公告)号：US20130134581A1

公开(公告)日：2013-05-30

申请号：US13308162

申请日：2011-11-30

申请人： Jing-Cheng LIN ,  Po-Hao TSAI

发明人： Jing-Cheng LIN ,  Po-Hao TSAI

IPC分类号： H01L23/498 ,  H01L21/50 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved.

摘要翻译： 用于形成凸块结构的机构减少了芯片和封装衬底之间的间隙的变化。 通过在电镀后对芯片和/或基板上的凸块结构上的焊料层进行平坦化，可以控制凸块结构的高度，以最小化晶片内部以及晶片位置，图案密度，晶粒尺寸和工艺变化中的变化。 结果，芯片和基板之间的间隔被控制得更均匀。 因此，底部填充质量得到改善。

公开(公告)号：US20120024456A1

公开(公告)日：2012-02-02

申请号：US12844113

申请日：2010-07-27

申请人： Yu-Liang LIN ,  Weng-Jin WU ,  Jing-Cheng LIN

发明人： Yu-Liang LIN ,  Weng-Jin WU ,  Jing-Cheng LIN

IPC分类号： B32B37/02 ,  B30B15/34

CPC分类号： H01L21/6835 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/6836 ,  H01L22/12 ,  H01L22/26 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

摘要： The embodiments described provide apparatus and methods for bonding wafers to carriers with the surface contours of plates facing the substrates or carriers are modified either by re-shaping, by using height adjusters, by adding shim(s), or by zoned temperature control. The modified surface contours of such plates compensate the effects that may cause the non-planarity of bonded substrates.

摘要翻译： 所描述的实施例提供了将晶片接合到载体上的装置和方法，其中面向基板或载体的板的表面轮廓通过重新成形，通过使用高度调节器，通过添加垫片或通过分区的温度控制来改变。 这种板的改进的表面轮廓补偿可能导致键合衬底的非平面性的影响。

公开(公告)号：US20130193593A1

公开(公告)日：2013-08-01

申请号：US13362913

申请日：2012-01-31

申请人： Jing-Cheng LIN ,  Cheng-Lin HUANG

发明人： Jing-Cheng LIN ,  Cheng-Lin HUANG

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L24/16 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014

摘要： The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.

摘要翻译： 用于形成凸块结构的机构能够在芯片和基板之间形成凸块结构，消除或降低焊料短路，焊剂残留物和底部填充物中的空隙的风险。 可以通过将结合的凸块结构中的铜柱的总高度除以接合的凸块结构的间距来限定的cc比率来限定下限，以避免短路。 也可以建立一个下限以排除芯片封装以避免焊剂残留和底部填充空隙形成。 此外，由于制造工艺限制，铜柱凸起的纵横比具有下限以避免不足的间隙和更高的极限。 通过遵循适当的凸块设计和工艺指南，芯片封装的产量和可靠性可能会增加。

公开(公告)号：US20110285005A1

公开(公告)日：2011-11-24

申请号：US12781960

申请日：2010-05-18

申请人： Yung-Chi LIN ,  Jing-Cheng LIN ,  Chen-Hua YU

发明人： Yung-Chi LIN ,  Jing-Cheng LIN ,  Chen-Hua YU

IPC分类号： H01L23/538

CPC分类号： H01L21/4857 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/19 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.

摘要翻译： 封装系统包括设置在插入器上的第一集成电路。 所述插入器包括至少一个包含穿过所述至少一个模塑复合层的多个电连接结构的模塑复合层。 第一互连结构设置在至少一个模塑复合层的第一表面上并与多个电连接结构电耦合。 第一集成电路与第一互连结构电耦合。

公开(公告)号：US20110001250A1

公开(公告)日：2011-01-06

申请号：US12825822

申请日：2010-06-29

申请人： Jing-Cheng LIN ,  Chen-Hua YU

发明人： Jing-Cheng LIN ,  Chen-Hua YU

IPC分类号： H01L23/488 ,  B05D5/12 ,  B32B3/00

CPC分类号： H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T428/24612 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/1146

摘要： A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer.

摘要翻译： 提供了一种用于金属间化合物（IMC）对Cu柱凸块的良好粘附的方法和结构。 该方法包括沉积Cu以形成Cu柱层，在Cu柱层的顶部上沉积扩散阻挡层，并在扩散阻挡层的顶部上沉积Cu覆盖层，其中形成金属间化合物（IMC） 扩散阻挡层，Cu覆盖层和位于Cu覆盖层顶部的焊料层。 IMC对Cu柱结构具有良好的粘附性，IMC的厚度可由Cu覆盖层的厚度控制，扩散阻挡层限制Cu从Cu柱层到焊料层的扩散。 该方法可以进一步包括在沉积Cu覆盖层之前在扩散阻挡层的顶部沉积薄层以获得润湿性。

公开(公告)号：US20130223014A1

公开(公告)日：2013-08-29

申请号：US13403511

申请日：2012-02-23

申请人： Jing-Cheng LIN ,  Po-Hao TSAI

发明人： Jing-Cheng LIN ,  Po-Hao TSAI

IPC分类号： H05K7/00 ,  B23K31/02

CPC分类号： H01L24/11 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates. Bumps are designed to have different widths to counter the higher plating current near edge(s) of dies or substrates. Bump sizes can be divided into different zones depending on the bump patterns and densities across the packaged die and/or substrates. Smaller bumps near edges reduce the thickness of plated film(s), which would have been thicker due to being near the edges. As a result, the bump heights across the packaged dies and/or substrates can be kept significantly constant and chip package can be properly formed.

摘要翻译： 用于在封装的芯片和封装衬底上形成凸点的机制减少了封装的裸片和封装的衬底上的凸起高度的变化。 冲击波被设计成具有不同的宽度以抵抗在模具或基底的边缘附近的较高电镀电流。 凸起尺寸可以分为不同的区域，这取决于包装模具和/或基底上的凸起图案和密度。 边缘附近的较小的凸起减小了镀膜的厚度，这将由于靠近边缘而变厚。 结果，穿过封装的管芯和/或衬底的突起高度可以保持显着恒定，并且可以适当地形成芯片封装。