公开(公告)号：US20210175130A1

公开(公告)日：2021-06-10

申请号：US17114826

申请日：2020-12-08

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Eugenio Dentoni Litta ,  Liping Zhang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: In one aspect, a method of forming a semiconducting device can comprise forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.

公开(公告)号：US20210028059A1

公开(公告)日：2021-01-28

申请号：US16934200

申请日：2020-07-21

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez ,  Anshul Gupta ,  Basoene Briggs

IPC: H01L21/768

Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

公开(公告)号：US20200168606A1

公开(公告)日：2020-05-28

申请号：US16696935

申请日：2019-11-26

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Steven Demuynck

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L21/3065

Abstract: The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

公开(公告)号：US20190271660A1

公开(公告)日：2019-09-05

申请号：US16292139

申请日：2019-03-04

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Jean-Francois de Marneffe ,  Chang Chen

IPC: G01N27/414 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  G01N33/487 ,  C12Q1/6869

Abstract: The disclosed technology generally relates to a method of forming a nanoscale opening in a semiconductor structure, and more particularly to forming a nanoscale opening that can be used for sensing the presence of polymers, e.g., the individual bases of deoxyribonucleic acid (DNA) or ribonucleic acid (RNA). In one aspect, a method of forming a nanopore in a semiconductor fin includes providing a fin structure comprising a bottom layer and a top layer, pattering the top layer to form a pillar, and laterally embedding the pillar in a filler material. The method additionally includes forming an aperture in the filler material by removing the pillar, and forming the nanopore in the bottom layer by etching through the aperture. In another aspect, a semiconductor fin is fabricated using the method.

公开(公告)号：US10192956B2

公开(公告)日：2019-01-29

申请号：US15204853

申请日：2016-07-07

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan ,  Min-Soo Kim ,  Doni Parnell ,  Roel Gronheid

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/66

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

公开(公告)号：US10079145B2

公开(公告)日：2018-09-18

申请号：US15292328

申请日：2016-10-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Arjun Singh

IPC: H01L21/47 ,  H01L21/027 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L21/0273 ,  G03F7/0002 ,  H01L21/02356 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/47 ,  H01L29/0692

Abstract: The present disclosure relates to a method for pattern formation on a substrate. An example embodiment includes a method for pattern formation. The method includes providing a photoresist layer on a composite substrate. The method also includes patterning the photoresist layer by lithography to define a plurality of parallel stripe photoresist structures. The method further includes providing a block copolymer on and along the composite substrate, in between the parallel stripe photoresist structures. The block copolymer includes a first component and a second component. The method additionally includes subjecting the block copolymer to predetermined conditions to cause phase separation of the first component and the second component. In addition, the method includes performing a sequential infiltration synthesis process. Still further, the method includes selectively removing the parallel stripe photoresist structures. Additionally, the method includes defining a core stripe structure. Even further, the method includes performing a self-aligned multiple patterning process.

公开(公告)号：US20180166534A1

公开(公告)日：2018-06-14

申请号：US15822275

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan ,  Soon Aik Chew

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02532 ,  H01L21/3065 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/775

Abstract: A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

公开(公告)号：US09905455B2

公开(公告)日：2018-02-27

申请号：US14919226

申请日：2015-10-21

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan

IPC: H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76807

Abstract: A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique.

公开(公告)号：US20170170313A1

公开(公告)日：2017-06-15

申请号：US15351504

申请日：2016-11-15

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Katia Devriendt ,  Rita Rooyackers

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  C30B29/40 ,  H01L21/02 ,  H01L29/66 ,  C30B25/04 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7827 ,  C30B25/04 ,  C30B29/06 ,  C30B29/08 ,  C30B29/40 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31138 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78642

Abstract: A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure that extends upwardly from a main surface of a substrate. The at least one protruding structure has a main portion of a first height and an upper portion on the main portion. The method also includes embedding the at least one protruding structure in a dielectric material. Further, the method includes removing at least an excess portion of the dielectric material, thereby exposing a top surface of the upper portion and forming a flattened surface of the top surface of the upper portion and the dielectric material. In addition, the method includes forming at least one cavity of a first depth by removing the upper portion, thereby exposing a top surface of the main portion of the at least one protruding structure.

公开(公告)号：US20170170007A1

公开(公告)日：2017-06-15

申请号：US15292328

申请日：2016-10-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Arjun Singh

IPC: H01L21/027 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L21/0273 ,  G03F7/0002 ,  H01L21/02356 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/47 ,  H01L29/0692

Abstract: The present disclosure relates to a method for pattern formation on a substrate. An example embodiment includes a method for pattern formation. The method includes providing a photoresist layer on a composite substrate. The method also includes patterning the photoresist layer by lithography to define a plurality of parallel stripe photoresist structures. The method further includes providing a block copolymer on and along the composite substrate, in between the parallel stripe photoresist structures. The block copolymer includes a first component and a second component. The method additionally includes subjecting the block copolymer to predetermined conditions to cause phase separation of the first component and the second component. In addition, the method includes performing a sequential infiltration synthesis process. Still further, the method includes selectively removing the parallel stripe photoresist structures. Additionally, the method includes defining a core stripe structure. Even further, the method includes performing a self-aligned multiple patterning process.