公开(公告)号：US07868410B2

公开(公告)日：2011-01-11

申请号：US12040350

申请日：2008-02-29

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： H01L21/70

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20100051474A1

公开(公告)日：2010-03-04

申请号：US12548893

申请日：2009-08-27

申请人： Panayotis C. Andricacos ,  Caliopi Andricacos ,  Donald F. Canaperi ,  Emanuel I. Cooper ,  John M. Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel C. Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew P. Mansson ,  Erick G. Walton ,  Alan C. West

发明人： Panayotis C. Andricacos ,  Caliopi Andricacos ,  Donald F. Canaperi ,  Emanuel I. Cooper ,  John M. Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel C. Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew P. Mansson ,  Erick G. Walton ,  Alan C. West

IPC分类号： B23H5/06

CPC分类号： C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

摘要翻译： 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：US07659200B2

公开(公告)日：2010-02-09

申请号：US11620391

申请日：2007-01-05

申请人： Guy Cohen ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Hariklia Deligianni

发明人： Guy Cohen ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Hariklia Deligianni

IPC分类号： H01L21/302

CPC分类号： C25D3/54 ,  B82Y10/00 ,  C25D5/022 ,  C25D7/123 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/02639 ,  Y10S977/762

摘要： A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.

摘要翻译： 提供包括锗的纳米结构，其包括直径小于1微米的导线和宽度小于1微米的与基底接触并从基底向外延伸的纳米结构以及制备方法。

公开(公告)号：US20090301890A1

公开(公告)日：2009-12-10

申请号：US12540710

申请日：2009-08-13

申请人： Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw

发明人： Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw

IPC分类号： C25D5/02 ,  C25D5/18

CPC分类号： C25D5/022 ,  B82Y25/00 ,  C25D3/562 ,  C25D5/10 ,  C25D5/18 ,  H01F1/0072 ,  H01F41/26 ,  Y10S977/762 ,  Y10S977/81 ,  Y10S977/838 ,  Y10T428/12028 ,  Y10T428/12465 ,  Y10T428/12493 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/12951 ,  Y10T428/12986 ,  Y10T428/24967 ,  Y10T428/2982

摘要： The present invention is related to a method for forming a structure that contains alternating first and second ferromagnetic layers of different material compositions. A substrate containing a supporting matrix with at least one open pore and a conductive base layer is first formed. Electroplating of the substrate is then carried out in an electroplating solution that contains at least one ferromagnetic metal element and one or more additional, different metal elements. A pulsed current with alternating high and low potentials is applied to the conductive base layer of the substrate structure to thereby form alternating ferromagnetic layers of different material compositions in the open pore of the supporting matrix.

摘要翻译： 本发明涉及一种用于形成包含不同材料组成的交替的第一和第二铁磁层的结构的方法。 首先形成含有具有至少一个开放孔的支撑基体和导电性基底层的基板。 然后在含有至少一种铁磁金属元素和一种或多种另外不同的金属元素的电镀溶液中进行基底的电镀。 具有交替的高电位和低电位的脉冲电流被施加到衬底结构的导电基底层，从而在支撑矩阵的开孔中形成不同材料组成的交替铁磁层。

公开(公告)号：US07602265B2

公开(公告)日：2009-10-13

申请号：US11163485

申请日：2005-10-20

申请人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

发明人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

IPC分类号： H01H51/22

CPC分类号： H01H59/0009

摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。

公开(公告)号：US07405154B2

公开(公告)日：2008-07-29

申请号：US11308433

申请日：2006-03-24

申请人： Cyril Cabral, Jr. ,  Hariklia Deligianni ,  Randolph F. Knarr ,  Sandra G. Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe M. Vereecken

发明人： Cyril Cabral, Jr. ,  Hariklia Deligianni ,  Randolph F. Knarr ,  Sandra G. Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe M. Vereecken

IPC分类号： H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

摘要翻译： 一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。 金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。 当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。 当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

公开(公告)号：US07405153B2

公开(公告)日：2008-07-29

申请号：US11306932

申请日：2006-01-17

申请人： Sandra G. Malhotra ,  Hariklia Deligianni ,  Stephen M. Rossnagel ,  Xiaoyan Shao ,  Tsong-Lin Tai ,  Oscar van der Straten

发明人： Sandra G. Malhotra ,  Hariklia Deligianni ,  Stephen M. Rossnagel ,  Xiaoyan Shao ,  Tsong-Lin Tai ,  Oscar van der Straten

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28562 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  Y10S438/952

摘要： A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein the second barrier layer is selected from the group consisting of ruthenium, platinum, palladium, rhodium and iridium and wherein the formation of the second barrier layer is manipulated so that the bulk concentration of oxygen in the second barrier layer is 20 atomic percent or less, and forming a conductive layer on the second barrier layer. The process may additionally include a step of treating the second barrier to reduce the amount of oxide on the surface of the second barrier layer.

摘要翻译： 一种在半导体结构中形成互连的方法，包括以下步骤：在衬底上形成电介质层，在电介质层上形成第一阻挡层，在第一阻挡层上形成第二阻挡层，其中第二阻挡层 选自钌，铂，钯，铑和铱，并且其中操作第二阻挡层的形成，使得第二阻挡层中的氧的体积浓度为20原子％以下，并且形成导电 层在第二阻挡层上。 该方法可以另外包括处理第二阻挡层以减少第二阻挡层表面上的氧化物的量的步骤。

公开(公告)号：US20080166584A1

公开(公告)日：2008-07-10

申请号：US11620480

申请日：2007-01-05

申请人： Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw

发明人： Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw

IPC分类号： H01F1/00 ,  C25D5/02 ,  B32B7/02

CPC分类号： C25D5/022 ,  B82Y25/00 ,  C25D3/562 ,  C25D5/10 ,  C25D5/18 ,  H01F1/0072 ,  H01F41/26 ,  Y10S977/762 ,  Y10S977/81 ,  Y10S977/838 ,  Y10T428/12028 ,  Y10T428/12465 ,  Y10T428/12493 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/12951 ,  Y10T428/12986 ,  Y10T428/24967 ,  Y10T428/2982

摘要： The present invention is related to a method for forming a structure that contains alternating first and second ferromagnetic layers of different material compositions. A substrate containing a supporting matrix with at least one open pore and a conductive base layer is first formed. Electroplating of the substrate is then carried out in an electroplating solution that contains at least one ferromagnetic metal element and one or more additional, different metal elements. A pulsed current with alternating high and low potentials is applied to the conductive base layer of the substrate structure to thereby form alternating ferromagnetic layers of different material compositions in the open pore of the supporting matrix.

摘要翻译： 本发明涉及一种用于形成包含不同材料组成的交替的第一和第二铁磁层的结构的方法。 首先形成含有具有至少一个开放孔的支撑基体和导电性基底层的基板。 然后在含有至少一种铁磁金属元素和一种或多种另外不同的金属元素的电镀溶液中进行基底的电镀。 具有交替的高电位和低电位的脉冲电流被施加到衬底结构的导电基底层，从而在支撑矩阵的开孔中形成不同材料组成的交替铁磁层。

公开(公告)号：US07190079B2

公开(公告)日：2007-03-13

申请号：US11265302

申请日：2005-11-03

申请人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

发明人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

摘要翻译： 通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。 提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

公开(公告)号：US20050127518A1

公开(公告)日：2005-06-16

申请号：US11047652

申请日：2005-02-02

申请人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

发明人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

IPC分类号： B32B15/04 ,  C25D3/56 ,  C25D9/08 ,  H01L21/288 ,  H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D9/08 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2224/05007

摘要： A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.