公开(公告)号：US20060180938A1

公开(公告)日：2006-08-17

申请号：US11258420

申请日：2005-10-26

申请人： Kazuaki Kurihara ,  Takeshi Shioga ,  John Baniecki

发明人： Kazuaki Kurihara ,  Takeshi Shioga ,  John Baniecki

IPC分类号： H01L23/48

CPC分类号： H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/76831 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/05091 ,  H01L2224/05096 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate so as to be electrically connected to the through vias; and multiple external connection terminals provided on a second main surface of the Si substrate so as to be electrically connected to the through vias. The second main surface faces away from the first main surface. The semiconductor chip is provided on one of the first main surface and the second main surface so as to be electrically connected to the through vias. The Si substrate has a thickness less than the diameter of the through holes.

摘要翻译： 公开了一种包括插入器和半导体芯片的半导体器件。 插入器包括Si衬底; 通过穿过Si衬底的相应通孔中的绝缘材料提供的多个通孔; 设置在所述Si衬底的第一主表面上以便与所述通孔电连接的薄膜电容器; 以及设置在Si衬底的第二主表面上的多个外部连接端子，以便电连接到通孔。 第二主表面远离第一主表面。 半导体芯片设置在第一主表面和第二主表面中的一个上，以便与通孔电连接。 Si衬底的厚度小于通孔的直径。

公开(公告)号：US07026680B2

公开(公告)日：2006-04-11

申请号：US10790760

申请日：2004-03-03

申请人： John David Baniecki ,  Takeshi Shioga ,  Kazuaki Kurihara

发明人： John David Baniecki ,  Takeshi Shioga ,  Kazuaki Kurihara

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L28/55 ,  H01L27/0805

摘要： An integrated thin film capacitive element comprising a dielectric material of the specified composition that exhibits increased voltage tunability of capacitance and capacitance density and a production process thereof are disclosed. The integrated thin film capacitive element comprises a capacitor structure constituted from a lower electrode, a dielectric layer comprised of the high dielectric constant material represented by the formula: (Ba(1-y)(1-x)Sr(1-y)xYy)Ti1+zO3+δ with the range 0

摘要翻译： 公开了一种集成的薄膜电容元件，其包括具有增加的电容和电容密度的电压可调谐性的特定组成的介电材料及其制造方法。 集成薄膜电容元件包括由下电极构成的电容器结构，由下式表示的高介电常数材料构成的介电层：（Ba（1-y）（1-x）） Sr 1（1-y）x Y y y）Ti 1 + z O 3 +δ，其范围为0 （1-y）（1-x）+ Sr（1-y）x <1，0.007

公开(公告)号：US20050142733A1

公开(公告)日：2005-06-30

申请号：US11066540

申请日：2005-02-28

申请人： Kazuaki Kurihara ,  Takeshi Shioga ,  John Baniecki

发明人： Kazuaki Kurihara ,  Takeshi Shioga ,  John Baniecki

IPC分类号： H01G4/33 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L21/8242

CPC分类号： H01G4/33 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/40

摘要： A thin film capacitor is provided which includes a single crystal high dielectric constant dielectric layer. The thin film capacitor has a single crystal silicon substrate, a single crystal intermediate layer epitaxially grown on the single crystal silicon substrate, a single crystal lower electrode epitaxially grown on the single crystal intermediate layer, a single crystal high dielectric constant dielectric layer epitaxially grown on the lower electrode layer, an upper electrode layer formed above the single crystal high dielectric constant dielectric layer, and a plurality of conductor terminals connected to the lower electrode layer and upper electrode layer at a plurality of positions.

摘要翻译： 提供了一种薄膜电容器，其包括单晶高介电常数介电层。 薄膜电容器具有单晶硅衬底，在单晶硅衬底上外延生长的单晶中间层，在单晶中间层外延生长的单晶下电极，外延生长在单晶硅介电层上的单晶高介电常数电介质层 下电极层，形成在单晶高介电常数介质层上的上电极层，以及在多个位置连接到下电极层和上电极层的多个导体端子。

公开(公告)号：US20050098816A1

公开(公告)日：2005-05-12

申请号：US10849791

申请日：2004-05-21

申请人： John Baniecki ,  Takeshi Shioga ,  Kazuaki Kurihara

发明人： John Baniecki ,  Takeshi Shioga ,  Kazuaki Kurihara

IPC分类号： H01G4/008 ,  H01G4/228 ,  H01G4/33 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/04 ,  H01L27/08 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/8244 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/20

CPC分类号： H01G4/33 ,  H01G4/008 ,  H01G4/228 ,  H01L21/28568 ,  H01L27/0805 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75 ,  H01L2224/11

摘要： The capacitor according to the present invention comprises a lower electrode 18 formed on a base substrate 14, a dielectric film 20 formed on the lower electrode 18, and an upper electrode 28 formed on the dielectric film 20 and including a polycrystalline conduction film 22, and a amorphous conduction film 24 formed on the polycrystalline conduction film 22. Because of the amorphous conduction film 24 included in the upper electrode 28, which can shut off hydrogen and water, hydrogen and water can be prohibited from arriving at the dielectric film 20. Accordingly, the dielectric film 20 of an oxide is prevented from being reduced with hydrogen, and the capacitor can have good electric characteristics.

摘要翻译： 根据本发明的电容器包括形成在基底基板14上的下电极18，形成在下电极18上的电介质膜20和形成在电介质膜20上并包括多晶导体膜22的上电极28，以及 形成在多晶导体膜22上的非晶导体膜24.由于包含在上电极28中的可以截断氢和水的非晶导体膜24，可以禁止氢和水到达电介质膜20。 ，防止氧化物的电介质膜20被氢还原，电容器可以具有良好的电特性。

公开(公告)号：US20050056878A1

公开(公告)日：2005-03-17

申请号：US10974747

申请日：2004-10-28

申请人： Takeshi Shioga ,  John Baniecki ,  Kazuaki Kurihara

发明人： Takeshi Shioga ,  John Baniecki ,  Kazuaki Kurihara

IPC分类号： H01G4/33 ,  H01L21/02 ,  H01L21/768 ,  H01L23/50 ,  H01L27/01 ,  H01L27/108 ,  H01L27/13

CPC分类号： H01L27/016 ,  H01L21/76804 ,  H01L21/76895 ,  H01L23/50 ,  H01L27/13 ,  H01L28/40 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode layer and an upper electrode layer, and conductor members respectively connected to the lower electrode layer and the upper electrode layer, wherein at least the dielectric layer has a side face having a sufficient slope for preventing the short circuit of the upper electrode layer with the lower electrode layer through the conductor member. A method of manufacturing such a thin film capacitor is also disclosed.

摘要翻译： 一种薄膜电容器，包括绝缘衬底，位于衬底上的电容器结构，具有夹在下电极层和上电极层之间的电介质层的电容器结构以及分别连接到下电极层和上电极的导体构件 其特征在于，至少所述电介质层的侧面具有足够的倾斜度，以防止通过所述导体部件的所述下部电极层的上部电极层的短路。 还公开了制造这种薄膜电容器的方法。

公开(公告)号：US08479386B2

公开(公告)日：2013-07-09

申请号：US12944904

申请日：2010-11-12

申请人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

发明人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

IPC分类号： H05K3/02

CPC分类号： H05K1/162 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/4605 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10378 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.

摘要翻译： 一种用于制造包括在半导体衬底上形成电容器的插入器的方法; 形成第一树脂层，其中第一部分电极埋在半导体衬底和电容器之上; 用切割工具切割第一部分电极和第一树脂层的上部; 形成具有埋在玻璃基板上的第二部分电极的第二树脂层，其中埋入有通孔; 用切割工具切割第二部分电极和第二树脂层的上部; 在使第一部分电极和第二部分电极彼此连接的同时，使第一树脂层和第二树脂层彼此粘合; 去除半导体衬底; 在玻璃基板上形成第三树脂层，覆盖电容器; 并在第三树脂层中埋设第三部分电极。

公开(公告)号：US08330480B2

公开(公告)日：2012-12-11

申请号：US12824896

申请日：2010-06-28

申请人： Takeshi Shioga ,  Kazuaki Kurihara

发明人： Takeshi Shioga ,  Kazuaki Kurihara

IPC分类号： G01R31/00

CPC分类号： G01R3/00 ,  G01R1/07378 ,  Y10T29/49155

摘要： Recesses are formed on one surface of a substrate. A conductive film covers an inner surface of each of the recesses. This conductive film contacts a bump of a semiconductor device to be inspected and is electrically connected to the bump. It is therefore possible to prevent damages of the bump to be caused by contact of a probe pin.

摘要翻译： 在基板的一个表面上形成凹部。 导电膜覆盖每个凹部的内表面。 该导电膜接触待检查的半导体器件的凸块并与凸点电连接。 因此，可以防止由于探针的接触引起的凸块的损坏。

公开(公告)号：US08058110B2

公开(公告)日：2011-11-15

申请号：US13043854

申请日：2011-03-09

申请人： Masataka Mizukoshi ,  Kanae Nakagawa ,  Takeshi Shioga ,  Kazuaki Kurihara ,  John David Baniecki

发明人： Masataka Mizukoshi ,  Kanae Nakagawa ,  Takeshi Shioga ,  Kazuaki Kurihara ,  John David Baniecki

IPC分类号： H01L21/76

CPC分类号： H01L24/91 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76801 ,  H01L21/7687 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48132 ,  H01L2224/73267 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/381 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2203/0195 ,  H05K2203/0228 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10 as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.

摘要翻译： 电镀方法包括在基板16上形成树脂层10的步骤; 用切割工具12切割树脂层10的表面部分的步骤; 通过无电解电镀在树脂层10上形成种子层36的步骤; 以及通过电镀在种子层36上形成电镀膜44的步骤。 可以赋予树脂层10的表面适当的粗糙度，由此能够充分确保种子层36与树脂层10之间的粘附性。 在树脂层10的表面没有形成过度的深孔，如通过去污处理，从而可以在树脂层10上形成光致抗蚀剂膜40的微粉化图案。因此，可以在 确保了高可靠性的窄间距树脂层10。

公开(公告)号：US07846852B2

公开(公告)日：2010-12-07

申请号：US12782867

申请日：2010-05-19

申请人： Takeshi Shioga ,  Masataka Mizukoshi ,  Kazuaki Kurihara

发明人： Takeshi Shioga ,  Masataka Mizukoshi ,  Kazuaki Kurihara

IPC分类号： H01L21/8238

CPC分类号： H05K1/162 ,  H01G9/025 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  Y10S438/957 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).

摘要翻译： 对于用于半导体集成电路元件的电极焊盘，用于信号传输的一些电极焊盘耦合到Ti膜。 用于信号传输的其他电极焊盘通过布线在多层布线中的布线耦合到电极焊盘。 用于电源的电极焊盘耦合到电极焊盘，电极彼此不同的电力线通过布线耦合到电极焊盘。 电极焊盘也耦合到铝箔（阳极）。 用于接地的电极焊盘耦合到接地线通过布线耦合到的电极焊盘。 电极焊盘也耦合到导电聚合物膜（阴极）。

公开(公告)号：US07795739B2

公开(公告)日：2010-09-14

申请号：US11984361

申请日：2007-11-16

申请人： Kazuaki Kurihara ,  Takeshi Shioga ,  John D. Baniecki

发明人： Kazuaki Kurihara ,  Takeshi Shioga ,  John D. Baniecki

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/76831 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/05091 ,  H01L2224/05096 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device is disclosed that includes an interposer and a semiconductor chip. The interposer includes a Si substrate; multiple through vias provided through an insulating material in corresponding through holes passing through the Si substrate; a thin film capacitor provided on a first main surface of the Si substrate so as to be electrically connected to the through vias; and multiple external connection terminals provided on a second main surface of the Si substrate so as to be electrically connected to the through vias. The second main surface faces away from the first main surface. The semiconductor chip is provided on one of the first main surface and the second main surface so as to be electrically connected to the through vias. The Si substrate has a thickness less than the diameter of the through holes.

摘要翻译： 公开了一种包括插入器和半导体芯片的半导体器件。 插入器包括Si衬底; 通过穿过Si衬底的相应通孔中的绝缘材料提供的多个通孔; 设置在所述Si衬底的第一主表面上以便与所述通孔电连接的薄膜电容器; 以及设置在Si衬底的第二主表面上的多个外部连接端子，以便电连接到通孔。 第二主表面远离第一主表面。 半导体芯片设置在第一主表面和第二主表面中的一个上，以便与通孔电连接。 Si衬底的厚度小于通孔的直径。