公开(公告)号：US20160155649A1

公开(公告)日：2016-06-02

申请号：US14585210

申请日：2014-12-30

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： WEI-NAN FANG ,  JIANN-SHIUN CHEN ,  TZU-YI CHUANG

IPC: H01L21/321 ,  H01L21/768 ,  H01L21/285 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/3212 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76877

Abstract: A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.

Abstract translation: 半导体器件的平坦化方法包括这里的步骤。 设置有基板，在其上形成有阻挡层。 在衬底中形成沟槽。 第一半导体膜被共形地沉积在停止层和沟槽上。 沉积第二半导体膜以填充沟槽并覆盖第一半导体膜。 执行化学机械抛光工艺，直到停止层暴露。 第一半导体膜上的化学机械抛光工艺的去除率高于第二半导体膜上的去除率。 选择性地去除衬底上的第一介电层。

公开(公告)号：US20160141420A1

公开(公告)日：2016-05-19

申请号：US14583771

申请日：2014-12-29

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： TAI-JU CHEN ,  YI-HAN YE ,  TE-CHIH CHEN

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/161 ,  H01L29/08 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L21/762 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L29/66704 ,  H01L21/02532 ,  H01L21/28035 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/407 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7851

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.

Abstract translation: 提供具有LDMOS结构的高电压FinFET器件及其制造方法。 高压FinFET器件包括：至少一个鳍结构，工作栅极，浅沟槽隔离结构和第一虚拟栅极。 翅片结构包括与第一类型阱区域相邻的第一类型阱区域和第二类型阱区域，并且还包括第一部分和第二部分。 沟槽设置在第一部分和第二部分之间并且设置在第一类型的区域中。 漏极掺杂层设置在设置在第一类型阱区域中的第一部分上，并且源极掺杂层设置在布置在第二类型阱区域中的第二部分上。 工作栅极设置在布置在第一类型阱区域和第二类型阱区域中的鳍结构上。

公开(公告)号：US20160093712A1

公开(公告)日：2016-03-31

申请号：US14515514

申请日：2014-10-16

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： SHIH-CHANG TSAI ,  TZU-CHIN TSENG ,  HSIAO-TING LIN ,  CHANG-YIH CHEN ,  SAM LAI

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/511 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/3212 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a first dielectric layer thereon. The first dielectric layer is provided with a trench. Then, a metal layer is formed to fill the trench and to cover the surface of the first dielectric layer. The metal layer is partially removed so that a remaining portion of the metal layer covers the first dielectric layer. A treatment process is performed to transform the remaining portion of the metal layer into a passivation layer on the top portion and a gate metal layer on the bottom portion. A chemical-mechanical polishing process is performed until the first dielectric layer is exposed so that a remaining portion of the passivation layer remains in the trench.

Abstract translation: 半导体器件及其制造方法。 该方法包括以下步骤。 衬底上设置有第一介电层。 第一电介质层设置有沟槽。 然后，形成金属层以填充沟槽并覆盖第一电介质层的表面。 金属层被部分去除，使得金属层的剩余部分覆盖第一介电层。 执行处理工艺以将金属层的剩余部分转变成顶部上的钝化层和底部上的栅极金属层。 执行化学 - 机械抛光工艺，直到暴露第一​​介电层，使得钝化层的剩余部分保留在沟槽中。

公开(公告)号：US09279923B2

公开(公告)日：2016-03-08

申请号：US13850297

申请日：2013-03-26

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Cheng-Hung Yu

IPC: G02B5/22 ,  G02B5/20 ,  G03F7/00

CPC classification number: G02B5/201 ,  G03F7/0007

Abstract: A method for fabricating a color filter layer, which is applied to an integrated circuit manufacturing process, includes the following steps. Firstly, a substrate is provided, and a groove structure is formed on the substrate. The groove structure includes a plurality of positive photoresist patterns and a plurality of trenches. Then, a first group of color filter patterns is formed in the trenches. The plurality of positive photoresist patterns is removed, so that a portion of a top surface of the substrate is exposed. Then, a second group of color filter patterns is formed on the exposed top surface of the substrate.

Abstract translation: 应用于集成电路制造工艺的制造滤色器层的方法包括以下步骤。 首先，设置基板，在基板上形成槽结构。 凹槽结构包括多个正光致抗蚀剂图案和多个沟槽。 然后，在沟槽中形成第一组滤色器图案。 去除多个正光致抗蚀剂图案，使得基板的顶表面的一部分被暴露。 然后，在曝光的基板的顶表面上形成第二组滤色器图案。

公开(公告)号：US20160043030A1

公开(公告)日：2016-02-11

申请号：US14477851

申请日：2014-09-04

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： CHIA-LIN LU ,  CHUN-LUNG CHEN ,  KUN-YUAN LIAO ,  FENG-YI CHANG

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76814 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first dielectric layer, and a first metal plug structure, wherein a circuit element is disposed on the substrate. The first dielectric layer is disposed on the circuit element and on the substrate. The first metal plug structure, including a first barrier metal layer and a first metal interconnector, is embedded in the first dielectric layer. The first metal interconnector is in direct contact with the circuit element. The first barrier metal layer is disposed on the first metal interconnector; wherein the first barrier metal layer and the first metal interconnect have different metal materials.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括衬底，第一介电层和第一金属插塞结构，其中电路元件设置在衬底上。 第一介电层设置在电路元件和基板上。 包括第一阻挡金属层和第一金属互连器的第一金属插塞结构被嵌入在第一电介质层中。 第一金属互连器与电路元件直接接触。 第一阻挡金属层设置在第一金属互连器上; 其中所述第一阻挡金属层和所述第一金属互连具有不同的金属材料。

公开(公告)号：US20160027885A1

公开(公告)日：2016-01-28

申请号：US14873194

申请日：2015-10-02

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kun-Yuan LO ,  Chih-Wei YANG ,  Cheng-Guo CHEN ,  Rai-Min HUANG ,  Jian-Cun KE

IPC: H01L29/423 ,  H01L21/324 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/265 ,  H01L21/28088 ,  H01L21/324 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.

Abstract translation: 提供了一种用于制造场效应晶体管的方法。 该方法包括：依次在基板上形成栅介质层和阻挡层; 在所述阻挡层上形成第一硅层并与所述阻挡层接触; 进行热处理以在所述阻挡层和所述第一硅层之间形成硅化物层; 以及在所述第一硅层上并与其接触形成第二硅层。

公开(公告)号：US20160027683A1

公开(公告)日：2016-01-28

申请号：US14457119

申请日：2014-08-12

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Ming-Shing Chen ,  Yu-Ting Wang ,  Ming-Hui Chang

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/32 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed.

Abstract translation: 半导体器件中的浅沟槽隔离结构及其制造方法。 该方法包括以下步骤。 衬底上设置衬垫氧化物层和其上的第一图案化的光刻胶层。 在对应于第一图案化光致抗蚀剂层的基板中形成第一沟槽。 第一介电层沉积在第一沟槽和衬底上。 提供第二图案化光致抗蚀剂层以在第一电介质层中形成开口，并且在衬底中形成对应于第二图案化光致抗蚀剂层的第二沟槽。 沉积覆盖衬底中的第一沟槽和第二沟槽的第二介电层以及衬底上的第一介电层。 第二电介质层通过化学机械抛光进行除去直到暴露第一​​介电层。 选择性地去除衬底上的第一介电层。

公开(公告)号：US20160020246A1

公开(公告)日：2016-01-21

申请号：US14332346

申请日：2014-07-15

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Shou-Guo WANG ,  Boon-Tiong Neo ,  Han-Chuan Fang

IPC: H01L27/146 ,  H01L21/306 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L27/14689 ,  H01L21/02065 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/1463

Abstract: The present invention provides a method for fabricating a CMOS image sensor including a plurality of steps. Firstly, a substrate is provided. Then, a pixel region covering most of the substrate and a logic circuit region on a periphery of the substrate are formed. After that, at least one trench is formed in the pixel region. Next, a deposition process is performed to fill the at least one trench and cover the pixel region. Then, a planarization process is performed to expose a surface of the pixel region. A first treatment on the exposed surface of the pixel region is next performed by applying a first cleaning solution including hydrogen fluoride (HF) and ethylene glycol (EG). Besides, an amount of HF is lesser than that of EG.

Abstract translation: 本发明提供一种制造包括多个步骤的CMOS图像传感器的方法。 首先，提供基板。 然后，形成覆盖基板的大部分的像素区域和基板的周围的逻辑电路区域。 之后，在像素区域中形成至少一个沟槽。 接下来，执行沉积处理以填充至少一个沟槽并覆盖像素区域。 然后，进行平坦化处理以使像素区域的表面露出。 接下来，通过施加包含氟化氢（HF）和乙二醇（EG）的第一清洗溶液来对像素区域的暴露表面进行第一处理。 此外，HF的量少于EG的量。

公开(公告)号：US09230954B1

公开(公告)日：2016-01-05

申请号：US14716925

申请日：2015-05-20

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chi-Hong Wu

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/0266 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a LDNMOS device for an ESD protection structure, by means of disposing a metal portion above the isolation portion and overlapping thereof, so as to protect the internal device from ESD more completely, comprising: a substrate; an ILD; a deep N-well region; a P-body region; a doped region, the doped region defines a diffusion area on the top thereof; a Poly gate electrode; an isolation structure disposed between the Poly gate electrode and the doped region; a contact portion connecting to the diffusion area of the doped region; and a metal portion disposed above the doped region, connecting to the contact portion. Wherein there is an overlap between the isolation structure and the metal portion, the direction of the overlap is parallel to the direction of channel length.

Abstract translation: 本发明提供了一种用于ESD保护结构的LDNMOS器件，其通过在隔离部分上方设置金属部分并与其重叠，以便更完全地保护内部器件免于ESD，包括：衬底; ILD; 深N井区; P体区域; 掺杂区域，掺杂区域在其顶部限定扩散区域; 多栅电极; 设置在所述多晶硅栅极和所述掺杂区域之间的隔离结构; 连接到掺杂区域的扩散区域的接触部分; 以及设置在掺杂区域上方的金属部分，连接到接触部分。 其中隔离结构和金属部分之间存在重叠，重叠的方向平行于沟道长度方向。

公开(公告)号：US09224696B2

公开(公告)日：2015-12-29

申请号：US14095980

申请日：2013-12-03

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Shih-Wei Li ,  Yun-Han Chu ,  Guo-Chih Wei

IPC: H01L23/00 ,  H01L23/14 ,  H01L21/02

CPC classification number: H01L23/562 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/0226 ,  H01L21/31116 ,  H01L21/481 ,  H01L21/76256 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L2224/83 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.

Abstract translation: 提供了一种集成半导体器件及其制造方法，其中集成半导体器件包括第一应力感应层，第二应力感应层和集成电路层。 第一应力诱导层覆盖在基底上。 第二应力诱导层部分地覆盖在第一应力诱导层上。 集成电路层结合在衬底上。