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292 条记录 (耗时 0.044 秒)

    In-situ accuracy control in flux dipping
    83.
    发明授权
    In-situ accuracy control in flux dipping 有权
    焊剂浸渍中的原位精度控制

    公开(公告)号：US08668131B2

    公开(公告)日：2014-03-11

    申请号：US13031040

    申请日：2011-02-18

    申请人： Yi-Li Hsiao ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chien Ling Hwang

    发明人： Yi-Li Hsiao ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chien Ling Hwang

    IPC分类号： B23K3/08 ,  B23K1/20

    CPC分类号： B23K1/203 ,  B23K3/082

    摘要： A flux dipping apparatus includes a flux plate having a top surface; and a dipping cavity in the flux plate and recessed from the top surface. A flux leveler is disposed over the flux plate and configured to move parallel to the top surface. A piezoelectric actuator is configured to adjust a distance between the flux leveler and the top surface in response to a controlling voltage applied to electrodes of the first piezoelectric actuator.

    摘要翻译： 焊剂浸渍装置包括具有顶表面的焊剂板; 以及在焊剂板中的浸入腔并且从顶表面凹陷。 助熔剂矫正器设置在焊剂板上方并且被配置成平行于顶表面移动。 压电致动器被配置为响应于施加到第一压电致动器的电极的控制电压来调节通量调节器和顶表面之间的距离。

    Self aligned air-gap in interconnect structures
    84.
    发明授权
    Self aligned air-gap in interconnect structures 有权
    互连结构中自对准气隙

    公开(公告)号：US08629560B2

    公开(公告)日：2014-01-14

    申请号：US12972228

    申请日：2010-12-17

    申请人： Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L29/40

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the air-gap; and a dielectric layer on the air-gap and the low-k dielectric layer.

    摘要翻译： 提供一种包括气隙的集成电路结构及其形成方法。 集成电路结构包括导线; 在导电线的侧壁上的自对准电介质层; 水平地邻接所述自对准介电层的气隙; 水平地邻接气隙的低k电介质层; 以及气隙和低k电介质层上的电介质层。

    Flip Chip Substrate Package Assembly and Process for Making Same
    88.
    发明申请
    Flip Chip Substrate Package Assembly and Process for Making Same 审中-公开
    倒装芯片基板封装组装及其制造方法

    公开(公告)号：US20120032337A1

    公开(公告)日：2012-02-09

    申请号：US12852196

    申请日：2010-08-06

    申请人： Chen-Fa Lu ,  Chen-Hua Yu ,  Chung-Shi Liu

    发明人： Chen-Fa Lu ,  Chen-Hua Yu ,  Chung-Shi Liu

    IPC分类号： H01L23/498 ,  H01L21/50 ,  H05K1/18

    CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/10674

    摘要： Apparatus and methods for providing a package substrate and assembly for a flip chip integrated circuit. A substrate is provided having a solder mask layer, openings in the solder mask layer for conductive bump pads, and openings in the solder mask layer between the conductive bump pads exposing a dielectric layer underneath the solder mask layer. A flip chip integrated circuit is attached to the substrate using a thermal reflow to reflow conductive solder bumps on the integrated circuit to the conductive bump pads. An underfill material is dispensed beneath the integrated circuit and physically contacting the dielectric layer of the substrate. In additional embodiments, one or more integrated circuits are flip chip mounted to the substrate. The resulting assembly has improved thermal characteristics over the assemblies of the prior art.

    摘要翻译： 用于提供用于倒装芯片集成电路的封装衬底和组件的装置和方法。 提供了一种衬底，其具有焊接掩模层，用于导电凸块焊盘的焊料掩模层中的开口，以及在焊料掩模层之间的焊料掩模层中的暴露出阻焊掩模层下面的介电层的开口。 使用热回流将倒装芯片集成电路附接到基板，以将集成电路上的导电焊料凸起回流到导电凸块焊盘。 底部填充材料被分配在集成电路下面并物理接触衬底的电介质层。 在另外的实施例中，将一个或多个集成电路倒装芯片安装到基板。 所得组件相对于现有技术的组件具有改善的热特性。

    METHODS FOR FORMING INTERCONNECT STRUCTURES THAT INCLUDE FORMING AIR GAPS BETWEEN CONDUCTIVE STRUCTURES
    89.
    发明申请
    METHODS FOR FORMING INTERCONNECT STRUCTURES THAT INCLUDE FORMING AIR GAPS BETWEEN CONDUCTIVE STRUCTURES 有权
    形成互连结构的方法，包括在导电结构之间形成空气GAPS

    公开(公告)号：US20110074038A1

    公开(公告)日：2011-03-31

    申请号：US12965078

    申请日：2010-12-10

    申请人： Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L23/52

    CPC分类号： H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76849 ,  H01L21/76867

    摘要： A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening.

    摘要翻译： 一种用于形成半导体结构的方法包括在衬底上形成牺牲层。 在牺牲层上形成第一介电层。 在牺牲层和第一介电层内形成多个导电结构。 牺牲层通过第一介电层进行处理，至少部分去除牺牲层并在两个导电结构之间形成至少一个气隙。 处理第一电介质层的表面，在形成气隙之后在第一介电层上形成第二电介质层。 在第二电介质层上形成第三电介质层。 至少一个开口形成在第三电介质层内，使得第二电介质层基本上保护第一电介质层不受形成开口的步骤的损害。

    Self-aligned air-gap in interconnect structures
    90.
    发明授权
    Self-aligned air-gap in interconnect structures 有权
    互连结构中的自对准气隙

    公开(公告)号：US07871923B2

    公开(公告)日：2011-01-18

    申请号：US11698565

    申请日：2007-01-26

    申请人： Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the air-gap; and a dielectric layer on the air-gap and the low-k dielectric layer.

    摘要翻译： 提供一种包括气隙的集成电路结构及其形成方法。 集成电路结构包括导线; 在导电线的侧壁上的自对准电介质层; 水平地邻接所述自对准介电层的气隙; 水平地邻接气隙的低k电介质层; 以及气隙和低k电介质层上的电介质层。