公开(公告)号：US20080128885A1

公开(公告)日：2008-06-05

申请号：US11565375

申请日：2006-11-30

申请人： Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

摘要： A stress decoupling structure provided underneath the under-ball-metallurgy (UBM) pads of a flip-chip bonding integrated circuit (IC) chip enhances the cyclic fatigue life of the solder joints formed by the solder bumps on the IC chip. The stress decoupling structure is formed from an elastic polymer layer provided over the active surface of the integrated circuit chip. A plurality of conductive metal posts are formed in the elastic polymer layer, extending between one of the contact pads on the active surface of the chip and one of the UBM pads. Solder bumps provided on the UBM pads form the solder joints between the chip and the next level interconnect structure.

摘要翻译： 在倒装芯片接合集成电路（IC）芯片的下球冶金（UBM）焊盘下面提供的应力去耦结构增强了由IC芯片上的焊料凸块形成的焊点的循环疲劳寿命。 应力去耦结构由设置在集成电路芯片的有源表面上的弹性聚合物层形成。 多个导电金属柱形成在弹性聚合物层中，在芯片的有效表面上的一个接触焊盘之一和UBM焊盘之一之间延伸。 UBM焊盘上提供的焊料凸块形成芯片和下一级互连结构之间的焊接点。

公开(公告)号：US20070257365A1

公开(公告)日：2007-11-08

申请号：US11777878

申请日：2007-07-13

申请人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

发明人： Szu Wei Lu ,  Hsin-Hui Lee ,  Ming-Chung Sung ,  Mirng-Ji Lii

IPC分类号： H01L23/48

CPC分类号： H01L21/78 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.

摘要翻译： 一种封装半导体芯片，包括具有低k电介质层和芯片基板的集成电路芯片，其中所述集成电路芯片的边缘具有第一边缘部分和第二边缘部分。 所述第一边缘部分的至少一部分与所述低k电介质层相同，并且所述第一边缘部分被激光烧蚀以在其中形成一系列圆形凹陷。 所述第二边缘部分与所述芯片基板的至少一部分处于相同的高度，并且所述第二边缘部分具有与所述第一边缘部分不同的表面纹理。 封装的半导体芯片还包括具有附接的集成电路芯片的封装基板和电连接在封装基板和集成电路芯片之间的多个焊料凸块。

公开(公告)号：US20070238220A1

公开(公告)日：2007-10-11

申请号：US11393050

申请日：2006-03-29

申请人： Mirng-Ji Lii ,  Szu Lu ,  Tjandra Karta ,  Chien-Hsiun Lee

发明人： Mirng-Ji Lii ,  Szu Lu ,  Tjandra Karta ,  Chien-Hsiun Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.

摘要翻译： 一种方法包括使用位于管芯和封装衬底或印刷电路板之间的多个焊料凸块将具有至少一个低k​​电介质层的集成电路管芯连接到封装衬底或印刷电路板。 低k电介质层的介电常数约为3.0或更小。 焊锡凸块的铅浓度约为5％以下。 在模具和封装衬底或印刷电路板之间形成分层的底部填充物。

公开(公告)号：US20050248019A1

公开(公告)日：2005-11-10

申请号：US10881605

申请日：2004-06-30

申请人： Te-Tsung Chao ,  Mirng-Ji Lii ,  Chung-Yi Lin ,  Abel Chang

发明人： Te-Tsung Chao ,  Mirng-Ji Lii ,  Chung-Yi Lin ,  Abel Chang

IPC分类号： H01L25/18 ,  H01L23/02 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29386 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/0102 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A stacked, multi-die semiconductor device and method of forming thereof. A preferred embodiment comprises disposing a stack of semiconductor dies to a substrate. The stacking arrangement is such that a lateral periphery of an upper die is cantilevered over a lower die thereby forming a recess. A supporting adhesive layer containing a filler is disposed upon the substrate about the lateral periphery of the lower die and substantially filling the recess. In one preferred embodiment, the filler comprises microspheres. In another preferred embodiment, the filler comprises a dummy die, an active die, or a passive die.

摘要翻译： 叠层多芯片半导体器件及其形成方法。 优选实施例包括将一叠半导体管芯设置到衬底上。 堆叠布置使得上模的侧边缘在下模上悬伸，从而形成凹部。 含有填料的支持粘合剂层设置在基体周围的下模的侧边周围并且基本上填充凹部。 在一个优选实施方案中，填料包括微球。 在另一个优选实施例中，填料包括虚设模具，活性模具或被动模具。

公开(公告)号：US09935038B2

公开(公告)日：2018-04-03

申请号：US13444649

申请日：2012-04-11

申请人： Tsung-Ding Wang ,  Hung-Jen Lin ,  Jiun Yi Wu ,  Mirng-Ji Lii ,  Chien-Hsun Lee

发明人： Tsung-Ding Wang ,  Hung-Jen Lin ,  Jiun Yi Wu ,  Mirng-Ji Lii ,  Chien-Hsun Lee

IPC分类号： H01L23/482 ,  H01L23/00 ,  H01L23/528 ,  H01L23/488 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L23/4824 ,  H01L21/563 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/05 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16056 ,  H01L2224/16146 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate.

公开(公告)号：US08823180B2

公开(公告)日：2014-09-02

申请号：US13493862

申请日：2012-06-11

申请人： Tsung-Ding Wang ,  Ming-Chung Sung ,  Jiun Yi Wu ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Tsung-Ding Wang ,  Ming-Chung Sung ,  Jiun Yi Wu ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012

摘要： Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die.

摘要翻译： 封装封装（PoP）器件和封装半导体管芯的方法被公开。 PoP器件包括底部封装的芯片，其具有设置在其顶表面上的焊球，以及顶部封装的管芯，其具有设置在其底表面上的金属突起凸块。 金属柱凸起包括凸起区域和耦合到凸起区域的尾部区域。 顶部封装模具上的每个金属柱形凸块与底部封装模具上的一个焊球相连。

公开(公告)号：US08610267B2

公开(公告)日：2013-12-17

申请号：US12840900

申请日：2010-07-21

申请人： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

发明人： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC分类号： H01L23/48

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/93 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81464 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.

公开(公告)号：US08409881B2

公开(公告)日：2013-04-02

申请号：US12941240

申请日：2010-11-08

申请人： William Cheng ,  Mirng-Ji Lii ,  Chen-Yung Ching ,  Hsin-Hui Lee

发明人： William Cheng ,  Mirng-Ji Lii ,  Chen-Yung Ching ,  Hsin-Hui Lee

IPC分类号： H01L21/66

CPC分类号： G06Q50/04 ,  Y02P90/30

摘要： A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type.

摘要翻译： 制造半导体晶片。 晶片具有多个管芯。 多个模具包括至少可操作的第一类型的可操作模具和不同于第一类型的第二类型的可操作模具。 第二类型的模具被使得不可操作，同时保持第一类型的模具可操作。 晶片在其上设置有第一类型的可操作模具和第二类型的不可操作模具，用于第一类型的模具的测试。

公开(公告)号：US08039315B2

公开(公告)日：2011-10-18

申请号：US12829017

申请日：2010-07-01

申请人： Hsin-Hui Lee ,  Mirng-Ji Lii ,  Chien-Hsiun Lee

发明人： Hsin-Hui Lee ,  Mirng-Ji Lii ,  Chien-Hsiun Lee

IPC分类号： H01L21/00

CPC分类号： H01L23/4334 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/19 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/03

摘要： A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate.

摘要翻译： 形成封装结构的方法包括提供多个管芯; 将多个模具附接到散热板上; 以及将所述散热板锯切成多个封装，每个封装包括所述多个管芯中的一个和所述散热板的一个。

公开(公告)号：US07846769B2

公开(公告)日：2010-12-07

申请号：US12639058

申请日：2009-12-16

申请人： Mirng-Ji Lii ,  Szu-Wei Lu ,  Tjandra Winata Karta ,  Chien-Hsiun Lee

发明人： Mirng-Ji Lii ,  Szu-Wei Lu ,  Tjandra Winata Karta ,  Chien-Hsiun Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.

摘要翻译： 一种方法包括使用位于管芯和封装衬底或印刷电路板之间的多个焊料凸块将具有至少一个低k​​电介质层的集成电路管芯连接到封装衬底或印刷电路板。 低k电介质层的介电常数约为3.0或更小。 焊锡凸块的铅浓度约为5％以下。 在模具和封装衬底或印刷电路板之间形成分层的底部填充物。