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    Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant subtrate for materials used to form the same
    81.
    发明申请
    Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant subtrate for materials used to form the same 审中-公开
    用于制造半导体结构和器件的结构和方法，其利用形成用于形成相同材料的材料制成合适的缓冲液

    公开(公告)号：US20030001207A1

    公开(公告)日：2003-01-02

    申请号：US09859700

    申请日：2001-05-16

    Applicant: Motorola, Inc.

    Inventor： Jamal Ramdani ,  Alexander A. Demkov ,  Lyndee L. Hilt

    IPC: H01L027/01

    CPC classification number: C30B25/18 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02538 ,  H01L21/0254

    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

    Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 实现顺应性衬底的形成的一种方式包括首先在硅晶片上生长容纳缓冲层。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。

    Structure and method for fabricating III-V nitride devices utilizing the formation of a compliant substrate
    82.
    发明申请
    Structure and method for fabricating III-V nitride devices utilizing the formation of a compliant substrate 审中-公开
    利用形成顺应性衬底来制造III-V族氮化物器件的结构和方法

    公开(公告)号：US20020149023A1

    公开(公告)日：2002-10-17

    申请号：US10161743

    申请日：2002-06-05

    Applicant: MOTOROLA, INC.

    Inventor： Lyndee L. Hilt ,  Jamal Ramdani

    IPC: H01L031/12

    CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02639 ,  H01L21/02647

    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer (202) on a silicon substrate (200). The accommodating buffer layer (202) is a layer of monocrystalline material spaced apart from the silicon substrate (200) by an amorphous interface layer (204) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Utilizing this technique permits the fabrication of semiconductor structures formed by high quality Group III-V nitride films.

    Abstract translation: 通过首先在硅衬底（200）上生长容纳缓冲层（202），可以将高质量的单晶材料外延层生长在大的硅晶片上。 容纳缓冲层（202）是通过氧化硅的非晶界面层（204）与硅衬底（200）间隔开的单晶材料层。 非晶界面层消耗应变并允许高质量单晶容纳缓冲层的生长。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 利用这种技术允许制造由高质量III-V族氮化物膜形成的半导体结构。

    GaN-based devices using (Ga, AL, In)N base layers
    85.
    发明授权
    GaN-based devices using (Ga, AL, In)N base layers 失效
    使用（Ga，AL，In）N基层的GaN基器件

    公开(公告)号：US6156581A

    公开(公告)日：2000-12-05

    申请号：US984473

    申请日：1997-12-03

    Applicant: Robert P. Vaudo ,  Joan M. Redwing ,  Michael A. Tischler ,  Duncan W. Brown

    Inventor： Robert P. Vaudo ,  Joan M. Redwing ,  Michael A. Tischler ,  Duncan W. Brown

    IPC: C30B33/00 ,  H01L21/205 ,  H01L33/00

    CPC classification number: C30B33/00 ,  B82Y15/00 ,  C30B23/02 ,  C30B25/02 ,  C30B25/18 ,  C30B29/36 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/0262 ,  H01L21/02664 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/0079 ,  Y10S117/915 ,  Y10T428/13 ,  Y10T428/21

    Abstract: A method of forming a (gallium, aluminum, indium) nitride base layer on a substrate for subsequent fabrication, e.g., by MOCVD or MBE, of a microelectronic device structure thereon. Vapor-phase (Ga, Al, In) chloride is reacted with a vapor-phase nitrogenous compound in the presence of the substrate, to form (Ga, Al, In) nitride. The (Ga, Al, In) nitride base layer is grown on the substrate by HVPE, to yield a microelectronic device base comprising a substrate with the (Ga, Al, In) nitride base layer thereon. The product of such HVPE process comprises a device quality, single crystal crack-free base layer of (Ga, Al, In) N on the substrate, in which the thickness of the base layer may, for example, be on the order of 2 microns and greater and the defect density of the base layer may, for example, be on the order of 1E8 cm.sup.-2 or lower. Microelectronic devices thereby may be formed on the base layer, over a substrate of a foreign (poor lattice match) material, such as sapphire. Devices which may be fabricated utilizing the HVPE base layer of the invention include light emitting diodes, detectors, transistors, and semiconductor lasers.

    Abstract translation: 在衬底上形成（镓，铝，铟）氮化物基底层的方法，用于例如通过MOCVD或MBE制造其上的微电子器件结构。 在衬底存在下，使气相（Ga，Al，In）与气相含氮化合物反应，形成（Ga，Al，In）氮化物。 （Ga，Al，In）氮化物基层通过HVPE在衬底上生长，得到包含其上具有（Ga，Al，In）氮化物基底层的衬底的微电子器件基底。 这种HVPE工艺的产物包括在衬底上的（Ga，Al，In）N的器件质量，单晶无裂纹基底层，其中基底层的厚度可以例如为2 微米和更大，并且基底层的缺陷密度可以例如为1E8cm-2或更低的数量级。 因此，微电子器件可以形成在基底层上，在诸如蓝宝石的外来（差的晶格匹配）材料的衬底上。 可以使用本发明的HVPE基层制造的器件包括发光二极管，检测器，晶体管和半导体激光器。

    Method for forming a high density quantum wire
    86.
    发明授权
    Method for forming a high density quantum wire 失效
    形成高密度量子线的方法

    公开(公告)号：US5833870A

    公开(公告)日：1998-11-10

    申请号：US833047

    申请日：1997-04-03

    Applicant: Sung Bock Kim ,  Jeong Rae Ro ,  El Hang Lee

    Inventor： Sung Bock Kim ,  Jeong Rae Ro ,  El Hang Lee

    IPC: H01L33/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/335 ,  H01L29/12 ,  H01L21/00

    CPC classification number: B82Y10/00 ,  H01L21/02439 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L29/125 ,  H01L29/66469

    Abstract: A method for forming a highly dense quantum wire, the method comprising the steps of: depositing a dielectric mask having dielectric patterns on the top surface of a semiconductor (100) substrate; forming the dielectric patterns in parallel to a (011) orientation on the semiconductor substrate; exposing a (111)B side and a(111)B side by chemical etching a selected region between the patterns so that the semiconductor substrate has a dove-tail shape; forming a buffer layer on the dove-tail semiconductor substrate; forming the first barrier layer on the buffer layer; forming a well layer on the first barrier layer; and forming the second barrier layer on the well layer.

    Abstract translation: 一种用于形成高密度量子线的方法，所述方法包括以下步骤：在半导体（100）衬底的顶表面上沉积具有电介质图案的电介质掩模; 在半导体衬底上形成平行于（011）取向的电介质图案; 通过化学蚀刻图案之间的选定区域来暴露（1 + E，ov 1 + EE 1）B侧和（11 + E，ov 1 + EE）B侧，使得半导体衬底具有鸽尾形状; 在鸽尾半导体衬底上形成缓冲层; 在缓冲层上形成第一阻挡层; 在所述第一阻挡层上形成阱层; 以及在所述阱层上形成所述第二阻挡层。

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