公开(公告)号：US20170154878A1

公开(公告)日：2017-06-01

申请号：US15342689

申请日：2016-11-03

申请人： Jae-Choon Kim ,  Eon-Soo Jang ,  Eun-Hee Jung ,  Hyon-Chol Kim ,  Byeong-Yeon Cho

发明人： Jae-Choon Kim ,  Eon-Soo Jang ,  Eun-Hee Jung ,  Hyon-Chol Kim ,  Byeong-Yeon Cho

IPC分类号： H01L25/10 ,  H01L25/00

CPC分类号： H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00

摘要： In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.

公开(公告)号：US20160084542A1

公开(公告)日：2016-03-24

申请号：US14961167

申请日：2015-12-07

申请人： JAE CHOON KIM ,  JICHUL KIM ,  Jin-Kwon BAE ,  EUNSEOK CHO

发明人： JAE CHOON KIM ,  JICHUL KIM ,  Jin-Kwon BAE ,  EUNSEOK CHO

IPC分类号： F25B21/02

CPC分类号： F25B21/02 ,  F25B2321/0212 ,  F25B2700/2107 ,  H01L35/32 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

摘要： A device includes a first board having a first area and a second area not overlapping the first area; and a thermoelectric semiconductor disposed between the first board and the second board at the first area of the first board configured to supply a voltage to the thermoelectric semiconductor; a package disposed at the second area of the first board.

摘要翻译： 一种装置包括具有第一区域和不与第一区域重叠的第二区域的第一板; 以及设置在所述第一板和所述第二板之间的热电半导体，所述热电半导体被配置为向所述热电半导体提供电压; 一个包装，设置在第一板的第二区域。

公开(公告)号：US20140247859A1

公开(公告)日：2014-09-04

申请号：US14136787

申请日：2013-12-20

申请人： Jae Choon KIM ,  Jichul KIM ,  Jin-Kwon BAE ,  Eunho JUNG

发明人： Jae Choon KIM ,  Jichul KIM ,  Jin-Kwon BAE ,  Eunho JUNG

IPC分类号： G01K7/01

CPC分类号： G01K7/42 ,  G01K3/06 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A semiconductor package includes a first package including a first substrate and a first semiconductor chip mounted on the first substrate and a second package facing and spaced apart from the first package. The second package includes a second substrate on which a second semiconductor chip is mounted. The semiconductor package also includes a connection structure electrically connecting the first and second packages to each other, a first temperature sensor connected to the first substrate, a second temperature sensor connected to the first semiconductor chip, and a third temperature sensor connected to the second semiconductor chip.

摘要翻译： 半导体封装包括第一封装，第一封装包括第一衬底和安装在第一衬底上的第一半导体芯片以及与第一封装相对并间隔开的第二封装。 第二封装包括其上安装有第二半导体芯片的第二基板。 半导体封装还包括将第一和第二封装彼此电连接的连接结构，连接到第一衬底的第一温度传感器，连接到第一半导体芯片的第二温度传感器和连接到第二半导体的第三温度传感器 芯片。

公开(公告)号：US20130139524A1

公开(公告)日：2013-06-06

申请号：US13692394

申请日：2012-12-03

申请人： Jae Choon KIM ,  Jichul KIM ,  Jin-Kwon BAE ,  Eunseok CHO

发明人： Jae Choon KIM ,  Jichul KIM ,  Jin-Kwon BAE ,  Eunseok CHO

IPC分类号： F25B21/02

CPC分类号： F25B21/02 ,  F25B2321/0212 ,  F25B2700/2107 ,  H01L35/32 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are thermoelectric cooling packages and thermal management methods thereof. The method may include measuring a temperature of the thermoelectric cooling package including a semiconductor chip and a thermoelectric cooler, comparing the temperature of the thermoelectric cooling package with a target temperature, operating the thermoelectric cooler when the temperature of the thermoelectric cooling package is higher than the target temperature, and stopping the operation of the thermoelectric cooler when the temperature of the thermoelectric cooling package becomes lower than the target temperature.

摘要翻译： 提供热电冷却封装及其热管理方法。 该方法可以包括测量包括半导体芯片和热电冷却器的热电冷却封装的温度，将热电冷却封装的温度与目标温度进行比较，当热电冷却封装的温度高于 目标温度，并且当热电冷却封装的温度变得低于目标温度时，停止热电冷却器的操作。

公开(公告)号：US09991245B2

公开(公告)日：2018-06-05

申请号：US14958928

申请日：2015-12-03

申请人： Jae Choon Kim ,  Donghan Kim ,  Jikho Song ,  Mitsuo Umemoto ,  Inho Choi

发明人： Jae Choon Kim ,  Donghan Kim ,  Jikho Song ,  Mitsuo Umemoto ,  Inho Choi

IPC分类号： H01L23/495 ,  H01L23/10 ,  H01L23/34 ,  H01L25/00 ,  H01L23/367 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package comprising: a semiconductor chip; a connection pillar that is disposed adjacent to the semiconductor chip; a first heat dissipation layer disposed on the semiconductor chip; and a second heat dissipation layer disposed on the first heat dissipation layer, the second heat dissipation layer including a first protrusion extending beyond a perimeter of the semiconductor chip and extending towards the connection pillar.

公开(公告)号：US20170207205A1

公开(公告)日：2017-07-20

申请号：US15406925

申请日：2017-01-16

申请人： Jichul KIM ,  Jae Choon KIM ,  Hansung RYU ,  KyongSoon CHO ,  YoungSang CHO ,  Yeo-Hoon YOON

发明人： Jichul KIM ,  Jae Choon KIM ,  Hansung RYU ,  KyongSoon CHO ,  YoungSang CHO ,  Yeo-Hoon YOON

IPC分类号： H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/04105 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

公开(公告)号：US09606591B2

公开(公告)日：2017-03-28

申请号：US13617619

申请日：2012-09-14

申请人： Heungkyu Kwon ,  Jae Choon Kim ,  Eunseok Cho ,  Jichul Kim

发明人： Heungkyu Kwon ,  Jae Choon Kim ,  Eunseok Cho ,  Jichul Kim

IPC分类号： G06F1/20

CPC分类号： G06F1/206 ,  G01J5/10 ,  G05B15/02

摘要： A surface temperature management method of mobile device is provided. The method includes sensing a temperature of an application processor in an operation mode of the mobile device; and controlling the application processor using the sensed temperature and a surface temperature management table to manage a surface temperature of a target part of the mobile device. The surface temperature management table includes information related to the temperature of the application processor corresponding to the surface temperature of the target part in the operation mode.

公开(公告)号：US20160204080A1

公开(公告)日：2016-07-14

申请号：US14958928

申请日：2015-12-03

申请人： Jae Choon KIM ,  Donghan KIM ,  Jikho SONG ,  Mitsuo UMEMOTO ,  Inho CHOI

发明人： Jae Choon KIM ,  Donghan KIM ,  Jikho SONG ,  Mitsuo UMEMOTO ,  Inho CHOI

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/367 ,  H01L23/31

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package comprising: a semiconductor chip; a connection pillar that is disposed adjacent to the semiconductor chip; a first heat dissipation layer disposed on the semiconductor chip; and a second heat dissipation layer disposed on the first heat dissipation layer, the second heat dissipation layer including a first protrusion extending beyond a perimeter of the semiconductor chip and extending towards the connection pillar.

摘要翻译： 一种半导体封装，包括：半导体芯片; 与所述半导体芯片相邻配置的连接柱; 设置在半导体芯片上的第一散热层; 以及设置在所述第一散热层上的第二散热层，所述第二散热层包括延伸超过所述半导体芯片的周边并朝向所述连接柱延伸的第一突起。

公开(公告)号：US20130166093A1

公开(公告)日：2013-06-27

申请号：US13617262

申请日：2012-09-14

申请人： Jae Choon Kim ,  Jichul Kim ,  Hyunggil Baek ,  Eunseok Cho

发明人： Jae Choon Kim ,  Jichul Kim ,  Hyunggil Baek ,  Eunseok Cho

IPC分类号： G05D23/00

CPC分类号： H01L23/34 ,  G06F1/203 ,  G06F1/206 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic device may be operated in any of a plurality of heat-dissipation modes to accommodate temperature rises, including rapid temperature rises, while allowing an electronic device to continue operating. A parameter such as clock frequency, a supply voltage, current consumption, the number of applications running, or other operating parameter, may be manipulated to control internal heat dissipation and thereby accommodate factors, such as external temperature rises. One operation mode may be a maximum operation mode in which clock(s) operate at their highest frequencies and power is supplied at its highest level. A shut-down operation mode, in which a processor cuts power to electronic components, may be entered when a temperature of interest exceeds a predetermined threshold.

摘要翻译： 电子设备可以以多种散热模式中的任何一种操作，以适应包括快速升温的温度上升，同时允许电子设备继续操作。 可以操纵诸如时钟频率，电源电压，电流消耗，运行数量或其他操作参数的参数以控制内部散热，从而适应诸如外部温度升高的因素。 一个操作模式可以是其中时钟以其最高频率操作并且在其最高电平提供功率的最大操作模式。 当感兴趣的温度超过预定阈值时，可以进入处理器切断电子部件的电源的关闭操作模式。

公开(公告)号：US20120133427A1

公开(公告)日：2012-05-31

申请号：US13240574

申请日：2011-09-22

申请人： Jae Choon Kim ,  Eunseok Cho ,  Mi-Na Choi ,  Kyoungsei Choi ,  Heejung Hwang ,  Seran Bae

发明人： Jae Choon Kim ,  Eunseok Cho ,  Mi-Na Choi ,  Kyoungsei Choi ,  Heejung Hwang ,  Seran Bae

IPC分类号： H01L27/00

CPC分类号： G05F1/463 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/16 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00

摘要： An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.

摘要翻译： 示例性实施例涉及一种包括半导体封装的半导体器件，其中半导体芯片安装在封装衬底上。 半导体封装可以包括温度测量装置和温度控制电路。 温度测量装置可以测量半导体封装的温度。 温度控制电路可以基于由温度测量装置测量的半导体封装的温度来改变半导体封装的操作速度。