公开(公告)号：US08571699B2

公开(公告)日：2013-10-29

申请号：US12879278

申请日：2010-09-10

申请人： Chen-Fa Lu ,  Cheng-Ting Chen ,  James Hu ,  Chung-Shi Liu

发明人： Chen-Fa Lu ,  Cheng-Ting Chen ,  James Hu ,  Chung-Shi Liu

IPC分类号： G06F19/00

CPC分类号： G05B19/41875 ,  B24B37/005

摘要： Processing defects arising during processing of a semiconductor wafer prior to back-grinding are reduced with systems and methods of sensor placement. One or more holes are bored into a chuck table for receiving semiconductor wafers, or a support table next to the chuck table. One or more sensors are disposed in the holes for monitoring parameters during a pre-back-grinding (PBG) process. A control box converts a set of signals received from the sensors. A computer-implemented process control tool receives the converted set of signals from the control box and determines whether the PBG process will continue.

摘要翻译： 通过传感器放置的系统和方法，减少了在后研磨之前处理半导体晶片期间产生的加工缺陷。 将一个或多个孔钻入用于接收半导体晶片的卡盘台，或者在卡盘台旁边的支撑台。 一个或多个传感器设置在孔中，用于在前置后研磨（PBG）过程期间监测参数。 控制箱转换从传感器接收的一组信号。 计算机实现的过程控制工具从控制箱接收转换的信号集，并确定PBG过程是否继续。

公开(公告)号：US08629053B2

公开(公告)日：2014-01-14

申请号：US12818890

申请日：2010-06-18

申请人： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

发明人： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/03831 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/93 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/3478 ,  H05K3/4007 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/1082

摘要： A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

摘要翻译： 提供了具有聚合物层的半导体器件及其制造方法。 用于聚合物层表面的两步等离子体处理包括使聚合物层的表面粗糙化并且使污染物松动的第一等离子体工艺，以及使聚合物层更平滑或使聚合物层变得粗糙的第二等离子体工艺。 可以在第一等离子体工艺和第二等离子体工艺之间使用蚀刻工艺，以除去由第一等离子体工艺松动的污染物。 在一个实施方案中，聚合物层通过原子力显微镜（AFM）测量的表面粗糙度在约1％至约8％之间，其表面积差异百分比（SADP）指数和/或具有小于约1的表面污染物 的Ti％，小于约1％的F，小于约1.5％的Sn和小于约0.4％的Pb。

公开(公告)号：US20110309490A1

公开(公告)日：2011-12-22

申请号：US12818890

申请日：2010-06-18

申请人： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

发明人： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/03831 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/93 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/3478 ,  H05K3/4007 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/1082

摘要： A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

摘要翻译： 提供了具有聚合物层的半导体器件及其制造方法。 用于聚合物层表面的两步等离子体处理包括使聚合物层的表面粗糙化并且使污染物松动的第一等离子体工艺，以及使聚合物层更平滑或使聚合物层变得粗糙的第二等离子体工艺。 可以在第一等离子体工艺和第二等离子体工艺之间使用蚀刻工艺，以除去由第一等离子体工艺松动的污染物。 在一个实施方案中，聚合物层通过原子力显微镜（AFM）测量的表面粗糙度在约1％至约8％之间，其表面积差异百分比（SADP）指数和/或具有小于约1的表面污染物 的Ti％，小于约1％的F，小于约1.5％的Sn和小于约0.4％的Pb。

公开(公告)号：US08716858B2

公开(公告)日：2014-05-06

申请号：US13167946

申请日：2011-06-24

申请人： Chen-Fa Lu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Chen-Fa Lu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： H01L23/48

CPC分类号： H01L24/03 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.

摘要翻译： 半导体器件包括在焊料凸块和钝化后互连（PPI）层之间的阻挡层。 阻挡层由无电镀镍（Ni）层，无电解钯（Pd）层或浸金（Au）层中的至少一种形成。

公开(公告)号：US08710458B2

公开(公告)日：2014-04-29

申请号：US12907711

申请日：2010-10-19

申请人： Yu-Hsiang Hu ,  Chen-Fa Lu ,  Chung-Shi Liu

发明人： Yu-Hsiang Hu ,  Chen-Fa Lu ,  Chung-Shi Liu

IPC分类号： B32B38/10 ,  H01L21/683

CPC分类号： H01L21/6836 ,  B32B2310/0831 ,  H01L21/67115 ,  H01L21/67132 ,  Y10T156/1917

摘要： A method of forming an integrated circuit includes providing a wafer, and a tape adhered to the wafer, wherein the tape has a main surface perpendicular to a first direction. The tape is exposed to a light to cause the tape to lose adhesion. In the step of exposing the tape, the wafer and the tape are rotated, and/or the light is tilt projected onto the tape, wherein a main projecting direction of the light and the first direction form a tilt angle greater than zero degrees and less than 90 degrees.

摘要翻译： 形成集成电路的方法包括提供晶片和粘附到晶片的带，其中带具有垂直于第一方向的主表面。 胶带暴露于光线，导致胶带失去粘合力。 在曝光胶带的步骤中，旋转晶片和胶带，和/或将光线投影到胶带上，其中，主要的光的投影方向和第一方向形成大于零度以下的倾斜角度 超过90度。

公开(公告)号：US08636559B2

公开(公告)日：2014-01-28

申请号：US13618836

申请日：2012-09-14

申请人： Chen-Fa Lu ,  Chiang-Hao Lee ,  Wei-Yu Chen ,  Chung-Shi Liu

发明人： Chen-Fa Lu ,  Chiang-Hao Lee ,  Wei-Yu Chen ,  Chung-Shi Liu

IPC分类号： B24B49/00 ,  B24B51/00

CPC分类号： H01L21/67265 ,  B24B7/228 ,  B24B41/061 ,  B24B49/16 ,  H01L21/304

摘要： A method of reducing manufacturing defects of semiconductor wafers during a back-grinding process. The method includes receiving a semiconductor wafer on a chuck table, wherein said chuck table has a surface upon which a front side of the wafer is placed, and wherein said chuck table has one or more holes in surface and one or more sensors placed in said one or more holes. The method further includes grinding at least a portion of a back side of the semiconductor wafer. The method further includes monitoring a parameter, while grinding, measured by the one or more sensors and adjusting the grinding based at least on the monitored parameter.

摘要翻译： 在后磨工序中减少半导体晶片的制造缺陷的方法。 该方法包括在卡盘台上接收半导体晶片，其中所述卡盘台具有放置晶片前侧的表面，并且其中所述卡盘台具有一个或多个表面孔，并且一个或多个传感器放置在所述 一个或多个孔。 该方法还包括研磨半导体晶片的背面的至少一部分。 该方法还包括在由一个或多个传感器测量的磨削过程中监测参数，并且至少基于所监测的参数来调整磨削。

公开(公告)号：US20120032337A1

公开(公告)日：2012-02-09

申请号：US12852196

申请日：2010-08-06

申请人： Chen-Fa Lu ,  Chen-Hua Yu ,  Chung-Shi Liu

发明人： Chen-Fa Lu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC分类号： H01L23/498 ,  H01L21/50 ,  H05K1/18

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/10674

摘要： Apparatus and methods for providing a package substrate and assembly for a flip chip integrated circuit. A substrate is provided having a solder mask layer, openings in the solder mask layer for conductive bump pads, and openings in the solder mask layer between the conductive bump pads exposing a dielectric layer underneath the solder mask layer. A flip chip integrated circuit is attached to the substrate using a thermal reflow to reflow conductive solder bumps on the integrated circuit to the conductive bump pads. An underfill material is dispensed beneath the integrated circuit and physically contacting the dielectric layer of the substrate. In additional embodiments, one or more integrated circuits are flip chip mounted to the substrate. The resulting assembly has improved thermal characteristics over the assemblies of the prior art.

摘要翻译： 用于提供用于倒装芯片集成电路的封装衬底和组件的装置和方法。 提供了一种衬底，其具有焊接掩模层，用于导电凸块焊盘的焊料掩模层中的开口，以及在焊料掩模层之间的焊料掩模层中的暴露出阻焊掩模层下面的介电层的开口。 使用热回流将倒装芯片集成电路附接到基板，以将集成电路上的导电焊料凸起回流到导电凸块焊盘。 底部填充材料被分配在集成电路下面并物理接触衬底的电介质层。 在另外的实施例中，将一个或多个集成电路倒装芯片安装到基板。 所得组件相对于现有技术的组件具有改善的热特性。

公开(公告)号：US20120091367A1

公开(公告)日：2012-04-19

申请号：US12907711

申请日：2010-10-19

申请人： Yu-Hsiang Hu ,  Chen-Fa Lu ,  Chung-Shi Liu

发明人： Yu-Hsiang Hu ,  Chen-Fa Lu ,  Chung-Shi Liu

IPC分类号： G01N21/01 ,  G21G5/00

CPC分类号： H01L21/6836 ,  B32B2310/0831 ,  H01L21/67115 ,  H01L21/67132 ,  Y10T156/1917

摘要： A method of forming an integrated circuit includes providing a wafer, and a tape adhered to the wafer, wherein the tape has a main surface perpendicular to a first direction. The tape is exposed to a light to cause the tape to lose adhesion. In the step of exposing the tape, the wafer and the tape are rotated, and/or the light is tilt projected onto the tape, wherein a main projecting direction of the light and the first direction form a tilt angle greater than zero degrees and less than 90 degrees.

摘要翻译： 形成集成电路的方法包括提供晶片和粘附到晶片的带，其中带具有垂直于第一方向的主表面。 胶带暴露于光线，导致胶带失去粘合力。 在曝光胶带的步骤中，旋转晶片和胶带，和/或将光线投影到胶带上，其中，主要的光的投影方向和第一方向形成大于零度以下的倾斜角度 超过90度。

公开(公告)号：US08298041B2

公开(公告)日：2012-10-30

申请号：US12900683

申请日：2010-10-08

申请人： Chen-Fa Lu ,  Chiang-Hao Lee ,  Wei-Yu Chen ,  Chung-Shi Liu

发明人： Chen-Fa Lu ,  Chiang-Hao Lee ,  Wei-Yu Chen ,  Chung-Shi Liu

IPC分类号： B24B49/00 ,  B24B51/00

CPC分类号： H01L21/67265 ,  B24B7/228 ,  B24B41/061 ,  B24B49/16 ,  H01L21/304

摘要： In a system or method for controlling wafer back-grinding, a chuck table has a surface for supporting a semiconductor wafer during a back-grinding process, one or more holes in the surface, and one or more sensors disposed in the one or more holes for monitoring a parameter during back-grinding. A computer-implemented process control tool is coupled to receive one or mote outputs from the one or more sensors and control the back-grinding process based on the received one or more outputs.

摘要翻译： 在用于控制晶片背面磨削的系统或方法中，卡盘台具有用于在后磨削过程中支撑半导体晶片的表面，表面中的一个或多个孔以及设置在一个或多个孔中的一个或多个传感器 用于在后研磨期间监测参数。 计算机实现的过程控制工具被耦合以从一个或多个传感器接收一个或微尘输出，并且基于所接收的一个或多个输出来控制背面磨削过程。

公开(公告)号：US09412689B2

公开(公告)日：2016-08-09

申请号：US13357379

申请日：2012-01-24

申请人： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

发明人： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC分类号： H01L23/02 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/0273 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/1131 ,  H01L2224/11424 ,  H01L2224/1152 ,  H01L2224/1162 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00014 ,  H01L2924/00

摘要： A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

摘要翻译： 提供一种用于封装半导体管芯的系统和方法。 实施例包括具有第一触点和第二触点的第一封装。 在第一接触件上形成接触后材料，以便调节接触垫之间的接头的高度，导体凸块。 在另一个实施例中，使用导电柱来控制接触垫和外部连接之间的接头的高度。