公开(公告)号：US20050093114A1

公开(公告)日：2005-05-05

申请号：US10900211

申请日：2004-07-28

申请人： Dae-Woo Son ,  Sa-Yoon Kang ,  Kwan-Jai Lee

发明人： Dae-Woo Son ,  Sa-Yoon Kang ,  Kwan-Jai Lee

IPC分类号： H01L21/60 ,  H01L23/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552 ,  H05K1/00 ,  H05K1/02

CPC分类号： H01L23/552 ,  H01L23/4985 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0393 ,  H05K2201/09772 ,  H05K2201/10681 ,  Y10T29/49121 ,  H01L2224/05599

摘要： A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.

摘要翻译： 带状电路基板和使用该电路基板的半导体装置以及形成带状电路基板的方法可以减少或消除电磁干扰（EMI），并提供能够提供更稳定的电源电压的基板或装置。 带状电路基板可以包括形成在绝缘膜上的绝缘膜和布线图案，以限定电子器件安装区域并且包括接地电极。 磁带电路基板可以包括形成在电子器件安装区域处的接地电极图案，以便除了接地电极图案连接到接地电极之外与布线图案绝缘。

公开(公告)号：US07339262B2

公开(公告)日：2008-03-04

申请号：US10900211

申请日：2004-07-28

申请人： Dae-Woo Son ,  Sa-Yoon Kang ,  Kwan-Jai Lee

发明人： Dae-Woo Son ,  Sa-Yoon Kang ,  Kwan-Jai Lee

IPC分类号： H01L23/495

CPC分类号： H01L23/552 ,  H01L23/4985 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0393 ,  H05K2201/09772 ,  H05K2201/10681 ,  Y10T29/49121 ,  H01L2224/05599

摘要： A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.

摘要翻译： 带状电路基板和使用该电路基板的半导体装置以及形成带状电路基板的方法可以减少或消除电磁干扰（EMI），并提供能够提供更稳定的电源电压的基板或装置。 带状电路基板可以包括形成在绝缘膜上的绝缘膜和布线图案，以限定电子器件安装区域并且包括接地电极。 磁带电路基板可以包括形成在电子器件安装区域处的接地电极图案，以便除了接地电极图案连接到接地电极之外与布线图案绝缘。

公开(公告)号：US06448661B1

公开(公告)日：2002-09-10

申请号：US10059932

申请日：2002-01-28

申请人： Hyeong-Seob Kim ,  Sa-Yoon Kang ,  Myung-Kee Chung ,  In-Ku Kang ,  Kwan-Jai Lee

发明人： Hyeong-Seob Kim ,  Sa-Yoon Kang ,  Myung-Kee Chung ,  In-Ku Kang ,  Kwan-Jai Lee

IPC分类号： H01L2348

CPC分类号： H01L24/83 ,  H01L23/481 ,  H01L24/29 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N−1) chip selection pads, an insulation layer, (N−1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

摘要翻译： 提供了一种具有在芯片级形成的芯片选择焊盘的三维多芯片封装及其制造方法。 通过堆叠多个（N）个半导体集成电路芯片来形成三维多芯片封装。 每个芯片包括集成电路管芯，芯片选择端子（N-1）芯片选择焊盘，绝缘层，（N-1）金属布线，上连接端子，下连接端子和沟槽布线。 每个芯片的芯片选择端通过在芯片级形成的芯片选择焊盘与其他芯片的芯片选择分离。

公开(公告)号：US07895742B2

公开(公告)日：2011-03-01

申请号：US11872580

申请日：2007-10-15

申请人： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

发明人： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

IPC分类号： H01K3/22

CPC分类号： H05K3/28 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0129 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

摘要： A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

摘要翻译： 根据本发明的制造带布线板的方法可以在形成布线图案中采用压印工艺，从而减少制造带布线板的工艺的数量，并允许制造工艺在单个生产线中进行。 因此，制造时间和成本可能降低。 布线图案的轮廓可以通过模具的印模图案的形状来确定。 这可以建立内部和外部引线的顶部宽度并且结合细小的垫间距。 虽然ILB和OLB过程可能使用NCP，但是由于软和弹性布线图案可能建立连接可靠性。

公开(公告)号：US07315086B2

公开(公告)日：2008-01-01

申请号：US11181145

申请日：2005-07-13

申请人： Dong-Han Kim ,  Sa-Yoon Kang ,  Seok-Won Lee

发明人： Dong-Han Kim ,  Sa-Yoon Kang ,  Seok-Won Lee

IPC分类号： H01L23/42 ,  H01L23/58 ,  H01L23/14

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/5384 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/11334 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/189 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/0401 ,  H01L2924/00012

摘要： A chip-on-board (COB) package has a flip chip assembly structure and is used for an integrated circuit (IC) card. The COB package has conductive patterns as contact terminals on an outer surface of a non-conductive film, and an IC chip on an inner surface of the film. The film has a number of holes through which the conductive patterns are partly exposed. A number of conductive bumps on an active surface of the IC chip face the inner surface of the film and enter corresponding holes in the non-conductive film to mechanically join and electrically couple to the conductive patterns. The disclosed COB package and a related manufacturing method allow a reduction in production cost, simplified process, better electrical connections, and improved reliability.

摘要翻译： 片上芯片（COB）封装具有倒装芯片组装结构，用于集成电路（IC）卡。 COB封装具有作为非导电膜的外表面上的接触端子的导电图案和膜的内表面上的IC芯片。 该膜具有多个孔，导电图案通过该孔部分露出。 IC芯片的有源表面上的多个导电凸块面向薄膜的内表面，并且在非导电薄膜中进入相应的孔以机械地连接并电耦合到导电图案。 所公开的COB封装和相关制造方法允许降低生产成本，简化工艺，更好的电连接和改进的可靠性。

公开(公告)号：US07190073B2

公开(公告)日：2007-03-13

申请号：US11158164

申请日：2005-06-20

申请人： Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee ,  Kyoung-Sei Choi

发明人： Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee ,  Kyoung-Sei Choi

IPC分类号： H01L23/48

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L23/49811 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H05K3/0032 ,  H05K3/323 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A circuit film having film bumps is provided for a film package. An IC chip is mechanically joined and electrically coupled to the circuit film through the film bumps instead of conventional chip bumps. In a fabrication method, a base film is partially etched by a laser to create an etched area that defines raised portion relatively raised from the etched area. Then a circuit pattern is selectively formed on the base film, partly running over the raised portions. The raised portion and the overlying circuit pattern constitute the film bumps having a height not greater than the height of the circuit film.

摘要翻译： 为薄膜封装提供具有膜凸块的电路薄膜。 IC芯片通过膜凸块机械连接并电耦合到电路膜，而不是传统的芯片凸块。 在制造方法中，通过激光部分地蚀刻基底膜以产生限定从蚀刻区域相对升高的凸起部分的蚀刻区域。 然后，在基膜上选择性地形成电路图案，部分地在凸起部分上运行。 凸起部分和上覆电路图案构成具有不大于电路膜高度的高度的膜凸块。

公开(公告)号：US20060091504A1

公开(公告)日：2006-05-04

申请号：US11256650

申请日：2005-10-21

申请人： Un-Byoung Kang ,  Chung-Sun Lee ,  Sa-Yoon Kang ,  Yong-Hwan Kwon

发明人： Un-Byoung Kang ,  Chung-Sun Lee ,  Sa-Yoon Kang ,  Yong-Hwan Kwon

IPC分类号： H01L23/58

CPC分类号： H05K3/3463 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/13144 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/8181 ,  H01L2224/81825 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/189 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： In one embodiment, a film circuit substrate comprises an insulating film made of polyimide resin; a conductive circuit pattern formed on the insulating film, the circuit pattern including an inner lead to be connected with a conductive bump of a semiconductor chip through a bump bonding process; and a tin-indium alloy layer formed on the inner lead to produce an inter-metallic compound layer of AuxSn composition during the bump bonding process.

摘要翻译： 在一个实施例中，薄膜电路基板包括由聚酰亚胺树脂制成的绝缘膜; 形成在所述绝缘膜上的导电电路图案，所述电路图案包括通过凸块接合工艺与半导体芯片的导电凸块连接的内部引线; 以及形成在内部引线上的锡铟合金层，以在凸点焊接工艺期间产生Au / Sn组分的金属间化合物层。

公开(公告)号：US20060012026A1

公开(公告)日：2006-01-19

申请号：US11173853

申请日：2005-06-30

申请人： Suk-Chae Kang ,  Sa-Yoon Kang ,  Dong-Han Kim ,  Si-Hoon Lee

发明人： Suk-Chae Kang ,  Sa-Yoon Kang ,  Dong-Han Kim ,  Si-Hoon Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a metal plate in which one or more openings are formed, the metal plate mounting a semiconductor chip and a printed wire pattern substrate, e.g. a PCB, mounting one or more decoupling capacitors. The semiconductor chip is in direct contact with the metal plate to improve thermal characteristics, and the substrate is supported by the metal plate to increase mechanical stability of the package. The one or more openings in the metal plate accommodate the passing therethrough of plural pins electrically connected via the printed wire pattern substrate to the semiconductor chip. The semiconductor package can be usefully applied to a digital micro-mirror device (DMD) semiconductor package for use in a projection display device.

摘要翻译： 半导体封装包括其中形成有一个或多个开口的金属板，安装半导体芯片的金属板和印刷的线图案衬底，例如， PCB，安装一个或多个去耦电容器。 半导体芯片与金属板直接接触以改善热特性，并且基板由金属板支撑以增加封装的机械稳定性。 金属板中的一个或多个开口适应通过印刷的线图案基板电连接到半导体芯片的多个引脚的穿过。 半导体封装可以有用地应用于用于投影显示装置的数字微镜器件（DMD）半导体封装。

公开(公告)号：US07329597B2

公开(公告)日：2008-02-12

申请号：US11261260

申请日：2005-10-28

申请人： Ye-Chung Chung ,  Dong-Han Kim ,  Sa-Yoon Kang

发明人： Ye-Chung Chung ,  Dong-Han Kim ,  Sa-Yoon Kang

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/49838 ,  H01L21/4839 ,  H01L23/49572 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.

摘要翻译： 具有包括周边区域和中心区域的活性表面的半导体芯片具有形成在周边区域的一部分上的连接区域。 半导体芯片包括形成在有源表面的周边区域中的输出焊盘和形成在有源表面的中心区域中的输入焊盘。 输入焊盘可以连接到通过连接区域的TAB磁带的布线图案。

公开(公告)号：US07183660B2

公开(公告)日：2007-02-27

申请号：US10949091

申请日：2004-09-23

申请人： Si-Hoon Lee ,  Sa-Yoon Kang ,  Dong-Han Kim

发明人： Si-Hoon Lee ,  Sa-Yoon Kang ,  Dong-Han Kim

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/49572 ,  H01L23/3157 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05599

摘要： A tape circuit substrate comprises a base film made of an insulating material, and a wiring pattern layer which is formed on the base film and has first leads that are connected to electrode pads arranged near a periphery of a semiconductor chip and second leads that are connected to electrode pads arranged near the center of the semiconductor chip. The semiconductor chip package comprises a semiconductor chip electrically bonded to the tape circuit substrate through chip bumps. In such a case, each of the leads is configured such that a tip end thereof to be bonded to the electrode pad has a width larger than that of a body portion thereof. According to the present invention, since the interval between the lead and the electrode pad can be made even narrower, a fine pitch semiconductor device can be realized.

摘要翻译： 带状电路基板包括由绝缘材料制成的基膜和形成在基膜上的布线图案层，并且具有连接到布置在半导体芯片的周围附近的电极焊盘的第一引线和连接的第二引线 到布置在半导体芯片的中心附近的电极焊盘。 半导体芯片封装包括通过芯片凸块电连接到带电路基板的半导体芯片。 在这种情况下，每个引线被构造成使得其与电极焊盘接合的前端的宽度大于其主体部分的宽度。 根据本发明，由于可以使引线与电极焊盘之间的间隔更窄，所以可以实现精细的间距半导体器件。