公开(公告)号：US08598048B2

公开(公告)日：2013-12-03

申请号：US13191783

申请日：2011-07-27

申请人： Kenneth Robert Rhyner ,  Peter R. Harper

发明人： Kenneth Robert Rhyner ,  Peter R. Harper

IPC分类号： H01L23/48

CPC分类号： H01L24/03 ,  H01L21/50 ,  H01L23/48 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.

摘要翻译： 包括半导体管芯和柔性电路（柔性电路）的集成电路封装以及用于形成集成电路封装的方法。 柔性电路可以包括不电耦合到有源迹线的直接连接焊盘，电耦合到直接连接焊盘的盲孔，以及具有接合焊盘的半导体管芯，其使用导体电连接到直接连接焊盘 。 接合焊盘，导体，直接连接焊盘和盲孔都可以垂直对准，每个都与另一个垂直对齐。

公开(公告)号：US20130026642A1

公开(公告)日：2013-01-31

申请号：US13191783

申请日：2011-07-27

申请人： Kenneth Robert Rhyner ,  Peter R. Harper

发明人： Kenneth Robert Rhyner ,  Peter R. Harper

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L24/03 ,  H01L21/50 ,  H01L23/48 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.

摘要翻译： 包括半导体管芯和柔性电路（柔性电路）的集成电路封装以及用于形成集成电路封装的方法。 柔性电路可以包括不电耦合到有源迹线的直接连接焊盘，电耦合到直接连接焊盘的盲孔，以及具有接合焊盘的半导体管芯，其使用导体电连接到直接连接焊盘 。 接合焊盘，导体，直接连接焊盘和盲孔都可以垂直对准，每个都与另一个垂直对齐。

公开(公告)号：US09564415B2

公开(公告)日：2017-02-07

申请号：US13618116

申请日：2012-09-14

申请人： Peter R. Harper

发明人： Peter R. Harper

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/16 ,  H01L25/16 ,  H01L23/31

CPC分类号： H01L24/94 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81986 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor package device is disclosed that includes a passive energy component integrated therein. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to the first surface. The semiconductor package device also includes a passive energy component positioned over the second surface. The passive energy component is electrically connected to one or more integrated circuits. The semiconductor package device also includes an encapsulation structure disposed over the second surface and at least substantially encapsulates the passive energy component.

摘要翻译： 公开了一种包括集成在其中的无源能量分量的半导体封装器件。 在一个实施方案中，半导体封装器件包括具有第一表面和第二表面的半导体衬底。 半导体衬底包括在第一表面附近形成的一个或多个集成电路。 半导体封装器件还包括位于第二表面上的被动能量分量。 被动能量分量电连接到一个或多个集成电路。 半导体封装器件还包括设置在第二表面上并且至少基本上封装被动能量部件的封装结构。

公开(公告)号：US08377746B2

公开(公告)日：2013-02-19

申请号：US13244364

申请日：2011-09-24

申请人： Peter R. Harper ,  Kenneth Maggio

发明人： Peter R. Harper ,  Kenneth Maggio

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L23/3128 ,  H01L23/5382 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48465 ,  H01L2224/49 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads.

摘要翻译： 包装封装（POP）包装前体及其包装的装置和系统包括包括导电层和顶表面的电子基板。 上表面的第一部分附着有IC芯片。 顶表面的第二部分在IC芯片的相对侧上具有多个第一附接焊盘，用于电耦合到IC芯片顶部上的第一电子器件。 顶表面的至少第三部分相对于第一和第二部分横向定位。 第三部分包括用于电耦合到至少第二电子设备的多个第二附接焊盘。 所述导电层中的至少一个包括耦合迹线，所述耦合迹线将所述多个第二附着焊盘中的至少一个耦合到所述IC裸片和/或所述多个第一附接焊盘中的一个或多个。

公开(公告)号：US20100006987A1

公开(公告)日：2010-01-14

申请号：US12169908

申请日：2008-07-09

申请人： Rajen Murugan ,  Kenneth R. Rhyner ,  Peter R. Harper ,  Souvik Mukherjee

发明人： Rajen Murugan ,  Kenneth R. Rhyner ,  Peter R. Harper ,  Souvik Mukherjee

IPC分类号： H01L23/552 ,  G06F17/50

CPC分类号： H01L23/552 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit (IC) device (200) includes an electronic substrate (201) having a plurality of layers (120) including at least one first electrically conductive layer and a lower surface dielectric layer. The IC device also includes an electrically conductive surface layer (126) disposed on the dielectric layer and coupled to a ground terminal (210) for the electronic substrate (201) for blocking electromagnetic interference (EMI). In the IC device, the conductive surface layer (126) includes an EMI shield region (204) over at least a portion of the dielectric layer. The EMI shield region (204) includes at least one solid area (206) and one or more adhesion areas (207) having a plurality of openings (208) arranged aperiodically in the adhesion areas (207).

摘要翻译： 集成电路（IC）装置（200）包括具有包括至少一个第一导电层和下表面电介质层的多个层（120）的电子基板（201）。 IC器件还包括设置在电介质层上并耦合到用于电子衬底（201）的用于阻挡电磁干扰（EMI）的接地端子（210）的导电表面层（126）。 在IC器件中，导电表面层（126）在电介质层的至少一部分上包括EMI屏蔽区域（204）。 EMI屏蔽区域（204）包括至少一个固体区域（206）和一个或多个粘附区域（207），其具有在粘附区域（207）中非周期地布置的多个开口（208）。

公开(公告)号：US07015585B2

公开(公告)日：2006-03-21

申请号：US10323296

申请日：2002-12-18

申请人： Susan H. Downey ,  Sheila F. Chopin ,  Peter R. Harper ,  Sohrab Safai ,  Tu-Anh Tran ,  Alan H. Woosley

发明人： Susan H. Downey ,  Sheila F. Chopin ,  Peter R. Harper ,  Sohrab Safai ,  Tu-Anh Tran ,  Alan H. Woosley

IPC分类号： H01L23/48

CPC分类号： H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32227 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.

摘要翻译： 使用封装基板封装集成电路，该封装基板的底侧具有规则的连接点阵列，顶部具有集成电路。 封装衬底还具有存在以提供顶侧和底侧之间的电连接的通孔。 通孔具有用于直接接收引线键的通孔捕获垫。 因此，从集成电路到顶侧的电线直接接触其捕获垫处的通孔。 在这样的连接中，不需要从导线在顶侧上粘合到通孔的位置的迹线。 这节省了成本。 此外，这使得封装衬底可用于多于一种类型的集成电路。

公开(公告)号：US06812580B1

公开(公告)日：2004-11-02

申请号：US10457632

申请日：2003-06-09

申请人： Robert J. Wenzel ,  Peter R. Harper

发明人： Robert J. Wenzel ,  Peter R. Harper

IPC分类号： H01L2348

CPC分类号： H01L24/06 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/0616 ,  H01L2224/06163 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/4554 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48092 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48233 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48601 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48701 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48801 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49052 ,  H01L2224/49096 ,  H01L2224/49097 ,  H01L2224/4912 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2224/49431 ,  H01L2224/854 ,  H01L2224/85401 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013

摘要： Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least 50 percent of the length of the shorter of the two adjacent wires. In one embodiment, the separation distance D is at most two times a diameter of the wire having the larger diameter of the two adjacent wires. In another embodiment, the separation distance D is at most three times a wire-to-wire pitch between the two adjacent wires. Each wire grouping may include two of more closely-spaced wires. Wire groupings of closely-spaced bonding wires may be used to form, for example, power-signal-ground triplets, signal-ground pairs, signal-power pairs, or differential signal pairs or triplets.

摘要翻译： 紧密间隔的接合线可用于各种不同的包装应用中，以实现改进的电气性能。 在一个实施例中，如果两条相邻导线之间的间隔距离D达到两条相邻导线中较短的长度的至少50％，则导线组内的两个相邻接合线是紧密间隔的。 在一个实施例中，分离距离D为具有两个相邻线的较大直径的线的直径的至多两倍。 在另一个实施例中，分离距离D至少为两条相邻线之间的线对线间距的三倍。 每个线分组可以包括两个更紧密间隔的导线。 紧密间隔的接合线的电线分组可用于形成例如功率 - 信号 - 接地三通态，信号 - 接地对，信号 - 功率对或差分信号对或三线态。

公开(公告)号：US08053349B2

公开(公告)日：2011-11-08

申请号：US12124305

申请日：2008-05-21

申请人： Kenneth R. Rhyner ,  Kevin Lyne ,  David G. Wontor ,  Peter R. Harper

发明人： Kenneth R. Rhyner ,  Kevin Lyne ,  David G. Wontor ,  Peter R. Harper

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (601), when the sites can be routed for metal plating (620). The space to place a maximum number (614) of signal routing traces is opened up by interrupting the periodicity of the site array from the edge (602) of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.

摘要翻译： 一种具有单金属层状基板的半导体倒装芯片球栅阵列封装（600）。 二维阵列的位置（611）可用于将信号（非共同网络分配）I / O类型的焊球附接到芯片区域（601）下方的基板，当位置可以路由为金属 电镀（620）。 通过从基板的边缘（602）朝向芯片下方的中心中断现场阵列的周期性来放置放置最大数量（614）的信号路由迹线的空间。 周期性优选地通过减少二维阵列的整个对齐线和行的中断。

公开(公告)号：US20090315156A1

公开(公告)日：2009-12-24

申请号：US12143199

申请日：2008-06-20

申请人： Peter R. Harper

发明人： Peter R. Harper

IPC分类号： H01L23/552 ,  H01L21/00

CPC分类号： H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Example packaged integrated circuit (IC) chips having conformal electromagnetic shields and methods to form the same are disclosed. A disclosed packaged IC chip comprises an IC attached to a first surface of a substrate, the substrate having a conductive pad on the first surface, a first conductive element electrically coupled to the conductive pad on the first surface of the substrate, a molding compound to encapsulate the IC and the first conductive element, the molding compound exposing a surface of the first conductive element, a conformal electromagnetic shield on the molding compound in electrical contact with the exposed surface of the first conductive element, and an externally exposed second conductive element attached to a second surface of the substrate, the second conductive element in electrical contact with the first conductive element.

摘要翻译： 公开了具有保形电磁屏蔽的实例封装集成电路（IC）芯片及其形成方法。 所公开的封装IC芯片包括附着到基板的第一表面的IC，所述基板在第一表面上具有导电焊盘，第一导电元件电耦合到基板的第一表面上的导电焊盘， 封装IC和第一导电元件，模制化合物暴露第一导电元件的表面，在与第一导电元件的暴露表面电接触的模制化合物上的共形电磁屏蔽以及附接的外部暴露的第二导电元件 到所述衬底的第二表面，所述第二导电元件与所述第一导电元件电接触。

公开(公告)号：US20090166889A1

公开(公告)日：2009-07-02

申请号：US11967844

申请日：2007-12-31

申请人： Rajen Murugan ,  Peter R. Harper ,  Mark Gerber

发明人： Rajen Murugan ,  Peter R. Harper ,  Mark Gerber

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Packaged integrated circuits having surface mount devices and methods to form the same are disclosed. A disclosed method comprises attaching an integrated circuit to a first side of a substrate, forming one or more first conductive elements on the substrate, attaching a surface mount device to a second side of the substrate via the first conductive elements, forming one or more second conductive elements on the second side of the substrate.

摘要翻译： 公开了具有表面贴装装置的封装集成电路及其形成方法。 所公开的方法包括将集成电路附接到衬底的第一侧，在衬底上形成一个或多个第一导电元件，经由第一导电元件将表面安装器件附接到衬底的第二侧，形成一个或多个第二 在基板的第二面上的导电元件。