公开(公告)号：US20110104888A1

公开(公告)日：2011-05-05

申请号：US12797837

申请日：2010-06-10

申请人： Ki-Hyuk KIM ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Seok-Ho Kim ,  Myeong-Soon Park ,  Chang-Woo Shin

发明人： Ki-Hyuk KIM ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Seok-Ho Kim ,  Myeong-Soon Park ,  Chang-Woo Shin

IPC分类号： H01L21/768

CPC分类号： H01L21/76813 ,  H01L21/561 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.

摘要翻译： 半导体器件及其形成方法，包括在芯片衬底上形成芯片焊盘，在芯片焊盘和芯片衬底上形成钝化层，在钝化层上形成第一绝缘层，形成凹槽和第一开口 所述第一绝缘层在所述钝化层中形成对应于所述第一开口的第二开口，在所述凹部，所述第一开口和所述第二开口的再分布线区域中形成再分配线，在所述再分布上形成第二绝缘层 线和第一绝缘层，并且在第二绝缘体中形成开口以将再分配线的一部分暴露为再分布焊盘。

公开(公告)号：US08431479B2

公开(公告)日：2013-04-30

申请号：US12797837

申请日：2010-06-10

申请人： Ki-Hyuk Kim ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Seok-Ho Kim ,  Myeong-Soon Park ,  Chang-Woo Shin

发明人： Ki-Hyuk Kim ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Seok-Ho Kim ,  Myeong-Soon Park ,  Chang-Woo Shin

IPC分类号： H01L21/4763

CPC分类号： H01L21/76813 ,  H01L21/561 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.

摘要翻译： 半导体器件及其形成方法，包括在芯片衬底上形成芯片焊盘，在芯片焊盘和芯片衬底上形成钝化层，在钝化层上形成第一绝缘层，形成凹槽和第一开口 所述第一绝缘层在所述钝化层中形成对应于所述第一开口的第二开口，在所述凹部，所述第一开口和所述第二开口的再分布线区域中形成再分配线，在所述再分布上形成第二绝缘层 线和第一绝缘层，并且在第二绝缘体中形成开口以将再分配线的一部分暴露为再分布焊盘。

公开(公告)号：US20100285635A1

公开(公告)日：2010-11-11

申请号：US12840656

申请日：2010-07-21

申请人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

发明人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC分类号： H01L21/60 ,  H01L21/50

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

摘要： A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

摘要翻译： 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US08088648B2

公开(公告)日：2012-01-03

申请号：US12840656

申请日：2010-07-21

申请人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

发明人： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC分类号： H01L21/50 ,  H01L21/60

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

摘要： A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

摘要翻译： 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US07638365B2

公开(公告)日：2009-12-29

申请号：US11623279

申请日：2007-01-15

申请人： Se-Young Jeong ,  Nam-Seog Kim ,  Cha-Jea Jo ,  Jong-Ho Lee ,  Myeong-Soon Park

发明人： Se-Young Jeong ,  Nam-Seog Kim ,  Cha-Jea Jo ,  Jong-Ho Lee ,  Myeong-Soon Park

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L27/146 ,  H01L27/148 ,  H01L23/02

CPC分类号： H01L23/3114 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2225/06524 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

摘要翻译： 提供一种堆叠式芯片封装及其形成方法。 间隔件形成在上芯片的一侧。 在间隔件上形成导线以电连接上芯片和下芯片。 堆叠式芯片封装的可靠性得到改善，因为引线接合不用于电连接上下芯片。 此外，堆叠的芯片封装的整体尺寸可以减小，因为接合线环的高度对整个堆叠的芯片封装高度没有贡献。

公开(公告)号：US07830017B2

公开(公告)日：2010-11-09

申请号：US11950251

申请日：2007-12-04

申请人： In-Young Lee ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Ho-Jin Lee ,  Myeong-Soo Park

发明人： In-Young Lee ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Ho-Jin Lee ,  Myeong-Soo Park

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

摘要翻译： 提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。 晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层 设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。

公开(公告)号：US07777345B2

公开(公告)日：2010-08-17

申请号：US12132925

申请日：2008-06-04

申请人： Ho-Jin Lee ,  Nam-Seog Kim ,  Yong-Chai Kwon ,  Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang

发明人： Ho-Jin Lee ,  Nam-Seog Kim ,  Yong-Chai Kwon ,  Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05561 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014

摘要： A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.

摘要翻译： 公开了一种具有通孔的半导体器件及其制造方法。 在一个实施例中，半导体器件包括形成在半导体衬底上的第一绝缘层。 具有用于露出第一绝缘层的一部分的第一孔的布线层形成在第一绝缘层上。 第二绝缘层形成在布线层的上部和第一孔中。 具有第二孔径以暴露第二绝缘层的一部分的导电焊盘形成在第二绝缘层上。 通过第一和第二绝缘层和半导体衬底的上部形成宽度比第一和第二孔的宽度窄的通孔。 在通孔中形成贯通电极。

公开(公告)号：US20080251939A1

公开(公告)日：2008-10-16

申请号：US12100359

申请日：2008-04-09

申请人： Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

发明人： Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

IPC分类号： H01L23/498

CPC分类号： H01L23/525 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01049

摘要： A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region.

摘要翻译： 提供了一种芯片堆叠封装，其中具有不同管芯尺寸的半导体芯片通过经由再分配工艺在划线区域中布置衬垫来堆叠，从而可以减小封装的厚度。 还提供了一种制造芯片堆叠封装的方法。 在芯片堆叠封装中，在基板的一个表面上布置多个电路图案，并且在其上安装单元半导体芯片。 单元半导体芯片包括顺序堆叠在基板上的多个半导体芯片。 单元半导体芯片的半导体芯片具有不同的管芯尺寸。 半导体芯片中的一个包括布置在第一芯片区域中的多个第一焊盘，并且其它半导体芯片包括布置在由划线区域限定的第二芯片区域的外侧的划线区域中的第二焊盘。

公开(公告)号：US07948089B2

公开(公告)日：2011-05-24

申请号：US12100359

申请日：2008-04-09

申请人： Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

发明人： Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

IPC分类号： H01L23/48

CPC分类号： H01L23/525 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01049

摘要： A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region.

摘要翻译： 提供了一种芯片堆叠封装，其中具有不同管芯尺寸的半导体芯片通过经由再分配工艺在划线区域中布置衬垫来堆叠，从而可以减小封装的厚度。 还提供了一种制造芯片堆叠封装的方法。 在芯片堆叠封装中，在基板的一个表面上布置多个电路图案，并且在其上安装单元半导体芯片。 单元半导体芯片包括顺序堆叠在基板上的多个半导体芯片。 单元半导体芯片的半导体芯片具有不同的管芯尺寸。 半导体芯片中的一个包括布置在第一芯片区域中的多个第一焊盘，并且其它半导体芯片包括布置在由划线区域限定的第二芯片区域的外侧的划线区域中的第二焊盘。

公开(公告)号：US07598607B2

公开(公告)日：2009-10-06

申请号：US12123367

申请日：2008-05-19

申请人： Hyun-Soo Chung ,  Dong-Hyeon Jang ,  Nam-Seog Kim ,  Sun-Won Kang

发明人： Hyun-Soo Chung ,  Dong-Hyeon Jang ,  Nam-Seog Kim ,  Sun-Won Kang

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

摘要： Provided is a semiconductor package with enhanced joint reliability and methods of fabricating the same. The method includes: forming package units including a semiconductor chip interposed between a bottom layer and a top layer; and sequentially stacking the package units on a substrate. The bottom layer and the top layer are formed of a material having a lower modulus than the semiconductor chip. The semiconductor package includes: at least one package unit disposed on a substrate, the package unit including a semiconductor chip having a pad, a bottom layer and a top layer substantially surrounding the semiconductor chip, and a redistribution structure overlying the top layer. The redistribution structure is electrically connected to the pad.

摘要翻译： 提供了具有增强的接头可靠性的半导体封装以及其制造方法。 该方法包括：形成包括插入在底层和顶层之间的半导体芯片的封装单元; 并且将所述封装单元依次堆叠在基板上。 底层和顶层由具有比半导体芯片低的模量的材料形成。 所述半导体封装包括：设置在基板上的至少一个封装单元，所述封装单元包括具有衬垫，底层和基本上围绕所述半导体芯片的顶层的半导体芯片以及覆盖所述顶层的再分布结构。 再分配结构电连接到焊盘。