公开(公告)号：US06867123B2

公开(公告)日：2005-03-15

申请号：US10250939

申请日：2001-11-30

申请人： Mitsuaki Katagiri ,  Yuji Shirai ,  Kunihiko Nishi ,  Takehiro Ohnishi

发明人： Mitsuaki Katagiri ,  Yuji Shirai ,  Kunihiko Nishi ,  Takehiro Ohnishi

IPC分类号： H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L27/02 ,  H01L27/105 ,  H01L21/44

CPC分类号： H01L24/02 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/10 ,  H01L24/13 ,  H01L27/0207 ,  H01L27/105 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor wafer which has finished formation of a relocating wiring layer thereon is stored and after determination of a design, solder bumps are formed over bump lands (one end of the relocating wiring layer) in accordance with a pattern which differs with a design, whereby a function or characteristic depending on the design is selected. The semiconductor wafer is then cut into a plurality of semiconductor chips, whereby a wafer level CSP is available.

摘要翻译： 存储已经完成其上定向布线层的半导体晶片，并且在设计确定之后，根据设计不同的图案，在凸起焊盘（重定位布线层的一端）上形成焊料凸点，由此 选择根据设计的功能或特性。 然后将半导体晶片切割成多个半导体芯片，由此可获得晶片级CSP。

公开(公告)号：US06946327B2

公开(公告)日：2005-09-20

申请号：US10771471

申请日：2004-02-05

申请人： Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshihide Yamaguchi

发明人： Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshihide Yamaguchi

IPC分类号： H01L21/3205 ,  H01L21/312 ,  H01L21/66 ,  H01L21/822 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/538 ,  H01L27/04 ,  H01L21/44

CPC分类号： H01L22/22 ,  H01L23/3114 ,  H01L23/5382 ,  H01L24/13 ,  H01L2223/54406 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/11 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05171

摘要： A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

摘要翻译： 半导体集成电路器件包括半导体衬底，形成在半导体衬底的一个主表面上并构成具有多个功能或多个特性的集成电路的电路元件，连接到集成电路的内部连接端子，用于 选择所述集成电路中的多种功能或特性之一，覆盖所述内部连接端子以使得内部连接端子被选择性地暴露的绝缘层和布置在所述绝缘层上的外部连接端子。 通过内部连接端子和外部连接端子之间的连接状态来选择多个功能中的一个或多个特性之一。

公开(公告)号：US06828174B2

公开(公告)日：2004-12-07

申请号：US10364318

申请日：2003-02-12

申请人： Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshiyuki Kado

发明人： Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshiyuki Kado

IPC分类号： H01L2144

CPC分类号： H01L21/6836 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： With respect to two types of chips to be mounted on a main surface of a package substrate, the ratio of chip area to the number of terminals of one chip and that of the other chip are compared with each other and the chip smaller in the ratio is mounted by the wire bonding method, while the chip larger in the ratio is mounted by the flip-chip method. It is possible to reduce the cost of manufacturing a multi-chip module wherein plural types of chips having different terminal pitches are mounted on a wiring substrate.

摘要翻译： 对于要安装在封装基板的主表面上的两种类型的芯片，将芯片面积与一个芯片的端子数与另一个芯片的端子数之比进行比较，并且芯片的比例越小 通过引线接合方式安装，而通过倒装芯片方法安装比例大的芯片。 可以降低制造具有不同端子间距的多种类型的芯片的多芯片模块的成本安装在布线基板上。

公开(公告)号：US06861742B2

公开(公告)日：2005-03-01

申请号：US10046446

申请日：2002-01-16

申请人： Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshihide Yamaguchi

发明人： Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshihide Yamaguchi

IPC分类号： H01L21/3205 ,  H01L21/312 ,  H01L21/66 ,  H01L21/822 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/538 ,  H01L27/04

CPC分类号： H01L22/22 ,  H01L23/3114 ,  H01L23/5382 ,  H01L24/13 ,  H01L2223/54406 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/11 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05171

摘要： A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

摘要翻译： 半导体集成电路器件包括半导体衬底，形成在半导体衬底的一个主表面上并构成具有多个功能或多个特性的集成电路的电路元件，连接到集成电路的内部连接端子，用于 选择所述集成电路中的多种功能或特性之一，覆盖所述内部连接端子以使得内部连接端子被选择性地暴露的绝缘层和布置在所述绝缘层上的外部连接端子。 通过内部连接端子和外部连接端子之间的连接状态来选择多个功能中的一个或多个特性之一。

公开(公告)号：US06841881B2

公开(公告)日：2005-01-11

申请号：US10132239

申请日：2002-04-26

申请人： Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshiyuki Kado

发明人： Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshiyuki Kado

IPC分类号： H01L25/18 ,  H01L21/60 ,  H01L25/065 ,  H01L25/07 ,  H01L29/40

CPC分类号： H01L21/6836 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： With respect to two types of chips to be mounted on a main surface of a package substrate, the ratio of chip area to the number of terminals of one chip and that of the other chip are compared with each other and the chip smaller in the ratio is mounted by the wire bonding method, while the chip larger in the ratio is mounted by the flip-chip method. It is possible to reduce the cost of manufacturing a multi-chip module wherein plural types of chips having different terminal pitches are mounted on a wiring substrate.

摘要翻译： 对于要安装在封装基板的主表面上的两种类型的芯片，将芯片面积与一个芯片的端子数与另一个芯片的端子数之比进行比较，并且芯片的比例越小 通过引线接合方式安装，而通过倒装芯片方法安装比例大的芯片。 可以降低制造具有不同端子间距的多种类型的芯片的多芯片模块的成本安装在布线基板上。

公开(公告)号：US20110156225A1

公开(公告)日：2011-06-30

申请号：US13062565

申请日：2009-07-31

申请人： Hiroshi Hozoji ,  Toshiaki Morita ,  Yusuke Yasuda ,  Chiko Yorita ,  Yuji Shirai

发明人： Hiroshi Hozoji ,  Toshiaki Morita ,  Yusuke Yasuda ,  Chiko Yorita ,  Yuji Shirai

IPC分类号： H01L23/552 ,  H01L21/56

CPC分类号： H01L23/3121 ,  H01L21/561 ,  H01L23/3677 ,  H01L23/552 ,  H01L23/66 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/165 ,  H01L2221/68331 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/0218 ,  H05K3/284 ,  H05K2201/0715 ,  H05K2201/0919 ,  H05K2203/1131 ,  H05K2203/1316 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor device achieving both electromagnetic wave shielding property and reliability in a heating process upon mounting electronic components. In the semiconductor device, mount devices 5 and 6 mounted on a main surface of a circuit board 1 are provided, the mount devices 5 and 6 are electrically connected to a wiring pattern 4 at the main surface of the circuit board 1, a sealant 7 of an insulating resin is formed to seal the mount devices 5 and 6, metal particles are applied to a surface of the sealant 7, and the metal particles applied are sintered, thereby forming an electromagnetic shielding layer 2, and electrically connecting the electromagnetic shielding layer 2 to a ground pattern 3 of the circuit board 1.

摘要翻译： 一种在安装电子元件时实现电加热过程中的电磁波屏蔽性和可靠性的半导体器件。 在半导体装置中，设置安装在电路基板1的主表面上的安装装置5和6，安装装置5和6在电路板1的主表面电连接到布线图案4，密封剂7 形成绝缘树脂以密封安装装置5和6，将金属颗粒施加到密封剂7的表面，并且将所施加的金属颗粒烧结，从而形成电磁屏蔽层2，并将电磁屏蔽层 2到电路板1的接地图案3。

公开(公告)号：US07583163B2

公开(公告)日：2009-09-01

申请号：US11891368

申请日：2007-08-10

申请人： Yasuo Osone ,  Chiko Yorita ,  Yuji Shirai ,  Seiichi Tomoi

发明人： Yasuo Osone ,  Chiko Yorita ,  Yuji Shirai ,  Seiichi Tomoi

IPC分类号： H03H9/00 ,  H03H9/205 ,  H01L41/08

CPC分类号： H03H3/04 ,  H03H9/564 ,  H03H9/589 ,  H03H2003/025

摘要： A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.

摘要翻译： 提供了能够以低成本一体地形成对应于同一芯片上的多个频带的SMR型声波滤波器的技术。 在包括对应于形成在同一芯片（基板）上的多个带的多个带通滤波器的SMR型声波滤波器中，形成声学多层膜，而不需要最少数量的掩模，并且共同形成具有不同厚度的压电薄膜。 例如，在以无掩模的方式在模具上形成在平台水田的深槽中的声学多层膜（低声阻抗层和高声阻抗层）之后，压电薄膜是c轴取向的， 并通过CMP方法等进行抛光，以对各个带的厚度进行调整，因此，在同一芯片上形成多个带的SMR型声波滤波器。

公开(公告)号：US4694418A

公开(公告)日：1987-09-15

申请号：US714809

申请日：1985-03-22

申请人： Fumio Ueno ,  Takeshi Yamakawa ,  Yuji Shirai

发明人： Fumio Ueno ,  Takeshi Yamakawa ,  Yuji Shirai

IPC分类号： G06G7/14 ,  G06N7/04 ,  H01L27/06 ,  H03K19/00 ,  H03K19/094 ,  G06G7/00 ,  G06G7/12

CPC分类号： H03K19/00 ,  G06G7/14 ,  G06N7/043 ,  H01L27/0629 ,  H03K19/094 ,  Y10S706/90

摘要： A fuzzy logic circuit comprising a current mirror comprising an FET, a first input current source connected to the input side of the current mirror, a second input current source, a wired OR connected at its input side to the output side of the current mirror and to the second input current source, and an output terminal connected to the output side of the wired OR.

摘要翻译： 一种模糊逻辑电路，包括电流镜，其包括FET，连接到电流镜的输入侧的第一输入电流源，第二输入电流源，在其输入侧连接到电流镜的输出侧的有线OR，以及 到第二输入电流源，以及连接到有线OR的输出侧的输出端子。

公开(公告)号：US20100172116A1

公开(公告)日：2010-07-08

申请号：US12612699

申请日：2009-11-05

申请人： Chiko Yorita ,  Yoshihide Yamaguchi ,  Yuji Shirai ,  Yu Hasegawa

发明人： Chiko Yorita ,  Yoshihide Yamaguchi ,  Yuji Shirai ,  Yu Hasegawa

IPC分类号： H05K9/00 ,  H05K3/36

CPC分类号： H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/0052 ,  H05K3/181 ,  H05K3/284 ,  H05K9/0084 ,  Y10T29/49126 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.

摘要翻译： 一种屏蔽电子元件，包括布线板，安装在所述布线板的主表面上的至少一个半导体芯片，密封所述布线板的整个上表面的密封剂和形成在所述布线板上的镍（Ni） 提供密封剂的上表面。 在保护接线板的背面的状态下，使用高压CO 2形成在密封剂的上表面上的钯（Pd）预处理层上形成Ni镀膜，并与 布线板的接地布线层或与接地布线层的端部连接的接地（GND）连接通孔。

公开(公告)号：US5315482A

公开(公告)日：1994-05-24

申请号：US961394

申请日：1992-10-15

申请人： Akira Tanaka ,  Hiroichi Shinohara ,  Kazuji Yamada ,  Takao Ohba ,  Akira Yamagiwa ,  Hitoshi Yoshidome ,  Yuji Shirai ,  Toshio Hatada ,  Munehisa Kishimoto ,  Michiharu Honda

发明人： Akira Tanaka ,  Hiroichi Shinohara ,  Kazuji Yamada ,  Takao Ohba ,  Akira Yamagiwa ,  Hitoshi Yoshidome ,  Yuji Shirai ,  Toshio Hatada ,  Munehisa Kishimoto ,  Michiharu Honda

IPC分类号： H01L23/36 ,  H01L23/367 ,  H01L25/10 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/36 ,  H05K7/20

CPC分类号： H05K1/021 ,  H01L23/367 ,  H01L25/105 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/182 ,  H05K2203/049 ,  H05K3/0061 ,  H05K3/366

摘要： A semiconductor apparatus comprises a heat diffusing plate and a surface installing printed board. A semiconductor device of a high heat generation is installed on the heat diffusing plate. A surface installing package and chip parts are installed on both surfaces of the printed board. A through hole is formed at the center of the printed board so that the semiconductor device is located at the center. The heat diffusing plate on which the semiconductor device has been installed and the surface installing printed board are connected and integrated.

摘要翻译： 半导体装置包括热扩散板和表面安装印刷板。 在散热板上安装有高发热的半导体装置。 表面安装封装和芯片部件安装在印刷电路板的两个表面上。 在印刷电路板的中心形成通孔，使得半导体器件位于中心。 已经安装了半导体器件的散热板和表面安装印刷板连接并整合。