公开(公告)号：US6110755A

公开(公告)日：2000-08-29

申请号：US194733

申请日：1998-12-02

申请人： Shigetsugu Muramatsu ,  Hiroshi Miyagawa

发明人： Shigetsugu Muramatsu ,  Hiroshi Miyagawa

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L21/98 ,  H01L23/12 ,  H01L23/13 ,  H01L23/24 ,  H01L23/31 ,  H05K1/02 ,  H01L21/00

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3025

摘要： A method for producing semiconductor devices by mounting semiconductor chips 12 on a substrate 20 and resin-encapsulated the same is provided, wherein a plurality of semiconductor devices having a high reliability are simultaneously and efficiently obtained from a single large-sized substrate, comprising the steps of mounting a plurality of semiconductor chips 12 on the large-sized substrate 20 in correspondence to a plurality of unit substrates 20a formed thereon; resin-encapsulating the semiconductor chips 12 by filling a encapsulating resin 16 in the inside of the outer peripheral edge of the large-sized substrate 20; and cutting the large-sized substrate 20 thus resin-encapsulated together with the encapsulating resin 16 into individual unit substrates to obtain a plurality of resin-encapsulated semiconductor devices.

摘要翻译： PCT No.PCT / JP98 / 01546 Sec。 371日期1998年12月2日第 102（e）日期1998年12月2日PCT提交1998年4月3日PCT公布。 第WO98 / 44547号公报 日期1998年10月8日提供了一种通过将半导体芯片12安装在基板20上并对其进行树脂封装的半导体器件的制造方法，其中具有高可靠性的多个半导体器件可以从单个大尺寸 基板，包括以下步骤：对应于形成在其上的多个单元基板20a，将多个半导体芯片12安装在大尺寸基板20上; 通过在大尺寸基板20的外周边缘的内部填充封装树脂16来树脂封装半导体芯片12; 并将大尺寸基板20切割成与封装树脂16一起被树脂封装到单独的单元基板中，以获得多个树脂封装的半导体器件。

公开(公告)号：US20110316170A1

公开(公告)日：2011-12-29

申请号：US13166083

申请日：2011-06-22

申请人： Shigetsugu Muramatsu ,  Satoshi Sunohara

发明人： Shigetsugu Muramatsu ,  Satoshi Sunohara

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/15151 ,  H01L2924/00012 ,  H01L2924/00

摘要： A wiring substrate includes a wiring pattern in an uppermost layer that includes pads. A solder resist layer covers the wiring pattern. A recess exposes part of the wiring pattern from the solder resist layer to form pads. The solder resist layer includes a portion formed in a region corresponding to the recess, a portion formed outward from the recess, and a portion formed inward from the recess. The upper surface of the solder resist layer at the portion corresponding to the recess is higher than the upper surface of the pads but lower than the upper surfaces of the other portions of the solder resist layer.

摘要翻译： 布线基板包括在包括焊盘的最上层中的布线图案。 阻焊层覆盖布线图案。 凹陷使得阻焊层的部分布线图案露出以形成焊盘。 阻焊层包括形成在与凹部对应的区域中的部分，从凹部向外形成的部分和从凹部向内形成的部分。 阻焊层的与凹部对应的部分的上表面高于焊盘的上表面，但低于阻焊层的其它部分的上表面。

公开(公告)号：US20110253422A1

公开(公告)日：2011-10-20

申请号：US13150691

申请日：2011-06-01

申请人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

发明人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC分类号： H05K1/02

CPC分类号： H05K3/4007 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/025 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.

摘要翻译： 布线基板包括：形成在规定数量的底层布线层上的最上布线层，最上布线层的一部分露出并用作与要安装的部件连接的垫; 以及覆盖最上层布线层的绝缘树脂层，其中最上层布线层的部分的厚度大于其最大布线层的厚度。

公开(公告)号：US06628527B2

公开(公告)日：2003-09-30

申请号：US09741481

申请日：2000-12-20

申请人： Shigetsugu Muramatsu ,  Takuya Kazama

发明人： Shigetsugu Muramatsu ,  Takuya Kazama

IPC分类号： H05K702

CPC分类号： H01L23/13 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15331 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49135 ,  H01L2224/81 ,  H01L2224/05599

摘要： A unit interconnection substrate for mounting leadless type electronic parts on a mount substrate by superposing them on each other in two or more stages, comprising an insulating surface on the top surface of which an interconnection circuit with conductor pads and connection terminals is formed, depressions for holding electronic parts formed in a bottom surface of the insulating substrate, connection terminals provided on the bottom surface of the insulating substrate on the periphery of the depression, and connection terminals electrically connected to the connection terminals of the top surface of the insulating substrate via conductor via holes provided in the insulating substrate. Electronic parts are electrically connected to the conductor pads on the top surface of the insulating substrate, thereby to make it possible to mount the electronic parts on the insulating substrate. Together with this, holding of the electronic parts mounted on the mount substrate in the depressions of the bottom surface of the insulating substrate is made possible.

摘要翻译： 一种单元互连基板，用于通过将安装基板上的无引线型电子部件彼此叠置在两个或更多个阶段中来安装无引线型电子部件，所述两个或多个阶段包括在其顶表面上形成有与导体焊盘和连接端子的互连电路的绝缘表面， 保持形成在所述绝缘基板的底面的电子部件，设置在所述凹部的周围的所述绝缘基板的底面上的连接端子，以及通过导体电连接到所述绝缘基板的上表面的连接端子的连接端子 通孔设置在绝缘基板中。 电子部件电连接到绝缘基板的顶表面上的导体焊盘，从而可以将电子部件安装在绝缘基板上。 与此同时，能够将安装在安装基板上的电子部件保持在绝缘基板的底面的凹部中。

公开(公告)号：US06404214B1

公开(公告)日：2002-06-11

申请号：US09468060

申请日：1999-12-20

申请人： Shigetsugu Muramatsu ,  Michio Horiuchi ,  Takuya Kazama

发明人： Shigetsugu Muramatsu ,  Michio Horiuchi ,  Takuya Kazama

IPC分类号： G01R3102

CPC分类号： H05K1/112 ,  G01R31/2886 ,  H01L2224/16237 ,  H05K1/0393 ,  H05K3/06 ,  H05K3/325 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10734

摘要： A substrate for inspecting an electronic device used for an electrical test of the electronic device having bump-shaped connection terminals, comprises: opening sections, the diameter of each opening being determined so that a connection terminal can be inserted into and drawn out from the opening, are formed penetrating the insulating substrate in a region on one side of an insulating substrate on which the electronic device is mounted, corresponding to an arrangement of the connection terminals; and wiring patterns, each of which is composed of a pad section being exposed onto a bottom face of the opening so that the pad can come into contact with the connection terminal so as to accomplish electrical continuity, a connecting pad section formed in a region outside of the region in which the pad section is formed, which comes into contact with a contact terminal of an inspection device so as to accomplish electrical continuity, and a wiring section for electrically connecting the pad section with the connecting pad section, are formed on the other side of the insulating substrate.

摘要翻译： 一种用于检查用于具有凸起形连接端子的电子设备的电气测试的电子设备的基板，包括：开口部分，每个开口的直径被确定为使得连接端子能够从开口插入和拉出 对应于连接端子的布置，在安装有电子设备的绝缘基板的一侧的区域中穿过绝缘基板; 以及布线图案，每个布线图案由暴露于开口的底面的焊盘部分组成，使得焊盘能够与连接端子接触以实现电连续性;连接焊盘部分形成在外部区域 形成有与检查装置的接触端子接触以实现电连续性的形成有焊盘部的区域，以及用于将焊盘部与连接焊盘部电连接的布线部，形成在 绝缘基板的另一侧。

公开(公告)号：US08835773B2

公开(公告)日：2014-09-16

申请号：US12752692

申请日：2010-04-01

申请人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

发明人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC分类号： H05K1/16 ,  H05K7/00 ,  H05K3/34 ,  H01L23/498 ,  H01L21/56 ,  H05K3/00 ,  H01L23/31 ,  H05K3/30 ,  H05K1/11 ,  H05K3/24

CPC分类号： H05K3/3452 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15151 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/305 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/025 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of manufacturing a wiring board for use in mounting of an electronic component includes: forming an outermost wiring layer on a surface side where the electronic component is mounted; forming an insulating layer so as to cover the wiring layer; and forming a concave portion in the insulating layer. The concave portion is formed by removing, using a mask formed in a required shape by patterning, an exposed portion of the insulating layer in a step-like shape until a surface of a pad defined at a portion of the wiring layer is exposed. The concave portion is preferably formed by removing the portion of the insulating layer by sand blast.

摘要翻译： 制造电子部件安装用布线基板的方法包括：在安装有电子部件的表面侧形成最外层布线层; 形成绝缘层以覆盖所述布线层; 以及在所述绝缘层中形成凹部。 通过使用通过图案化形成所需形状的掩模，以阶梯状形状除去绝缘层的露出部分，直到露出布线层的一部分的焊盘的表面来形成凹部。 凹部优选通过用喷砂除去绝缘层的一部分而形成。

公开(公告)号：US08575495B2

公开(公告)日：2013-11-05

申请号：US13239630

申请日：2011-09-22

申请人： Shigetsugu Muramatsu ,  Satoshi Sunohara

发明人： Shigetsugu Muramatsu ,  Satoshi Sunohara

IPC分类号： H05K1/16 ,  H05K1/02

CPC分类号： H05K1/0269 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09918 ,  Y10T29/49155 ,  H01L2924/00

摘要： A wiring substrate includes a wiring pattern, which includes an upper surface forming a desired recognition mark, and a solder resist layer, which covers the wiring pattern. The solder resist layer includes a recess that entirely exposes the upper surface of the wiring pattern. The solder resist layer includes a solder resist layer formed at a region corresponding to the recess and a solder resist layer formed outside the recess. The recess entirely exposes the upper surface of the wiring pattern as the recognition mark, and the solder resist layer is formed at portions outside the upper surface of the wiring pattern.

摘要翻译： 布线基板包括覆盖布线图案的布线图案，其包括形成所需识别标记的上表面和阻焊层。 阻焊层包括完全暴露布线图案的上表面的凹部。 阻焊层包括在与凹部对应的区域形成的阻焊层和在凹部外形成的阻焊层。 凹部完全将布线图案的上表面暴露为识别标记，并且阻焊层形成在布线图案的上表面以外的部分。

公开(公告)号：US08222532B2

公开(公告)日：2012-07-17

申请号：US13150691

申请日：2011-06-01

申请人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

发明人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC分类号： H05K1/03 ,  H01K3/10

CPC分类号： H05K3/4007 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/025 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.

摘要翻译： 布线基板包括：形成在规定数量的底层布线层上的最上布线层，最上布线层的一部分露出并用作与要安装的部件连接的垫; 以及覆盖最上层布线层的绝缘树脂层，其中最上层布线层的部分的厚度大于其最大布线层的厚度。

公开(公告)号：US20080251279A1

公开(公告)日：2008-10-16

申请号：US11946360

申请日：2007-11-28

申请人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

发明人： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC分类号： H05K3/00 ,  H05K1/00

CPC分类号： H05K3/4007 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/025 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.

摘要翻译： 布线基板包括：形成在规定数量的底层布线层上的最上布线层，最上布线层的一部分露出并用作与要安装的部件连接的垫; 以及覆盖最上层布线层的绝缘树脂层，其中最上层布线层的部分的厚度大于其最大布线层的厚度。

公开(公告)号：US20070200211A1

公开(公告)日：2007-08-30

申请号：US11705402

申请日：2007-02-13

申请人： Tsuyoshi Kobayashi ,  Shigetsugu Muramatsu

发明人： Tsuyoshi Kobayashi ,  Shigetsugu Muramatsu

IPC分类号： H01L23/495

CPC分类号： H01L23/5226 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09645 ,  H05K2201/09827 ,  H01L2924/00

摘要： In the case in which an electrical connection between upper and lower layers is to be carried out through a via opening portion 16 provided on an insulating layer 14 of a wiring substrate constituting a multilayer wiring substrate, the electrical connection between the upper and lower layers is performed through a conductive material 30 while exposing a part of wall surfaces of the via opening portion 16 of the insulating layer without covering all of the wall surfaces of the via opening portion 16 with the conductive material 30.

摘要翻译： 在通过设置在构成多层布线基板的布线基板的绝缘层14上的通孔开口部16进行上下层之间的电连接的情况下，上层和下层之间的电连接是 同时通过绝缘层的通孔开口部分16的一部分壁表面暴露，而不用导电材料30覆盖通孔开口部分16的所有壁表面。