公开(公告)号：US10192780B1

公开(公告)日：2019-01-29

申请号：US15991529

申请日：2018-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaohan Wang ,  Jiehui Shu ,  Brendan O'Brien ,  Terry A. Spooner ,  Jinping Liu ,  Ravi Prakash Srivastava

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Methods of self-aligned double patterning and improved interconnect structures formed by self-aligned double patterning. A mandrel line including an upper layer and a lower layer is formed over a hardmask. A non-mandrel cut block is formed over a portion of a non-mandrel line, after which the upper layer of the mandrel line is removed. An etch mask is formed over a first section of the lower layer of the mandrel line defining a mandrel cut block over a first portion of the hardmask. The first section of the lower layer is arranged between adjacent second sections of the lower layer. The second sections of the lower layer of the mandrel line are removed to expose respective second portions of the hardmask, and the second portions of the hardmask are removed to form a trench. The mandrel cut block masks the first portion of the hardmask during the etching process.

公开(公告)号：US10115807B2

公开(公告)日：2018-10-30

申请号：US15343821

申请日：2016-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-Hwa Chi ,  Jinping Liu

IPC: H01L21/30 ,  H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the silicon germanium of the second portion that is below the gate structure.

公开(公告)号：US10056458B2

公开(公告)日：2018-08-21

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho Maeng ,  Andy Wei ,  Anthony Ozzello ,  Bharat Krishnan ,  Guillaume Bouche ,  Haifeng Sheng ,  Haigou Huang ,  Huang Liu ,  Huy M. Cao ,  Ja-Hyung Han ,  SangWoo Lim ,  Kenneth A. Bates ,  Shyam Pal ,  Xintuo Dai ,  Jinping Liu

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US09577066B1

公开(公告)日：2017-02-21

申请号：US15054314

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Fuad Al-Amoody ,  Jinping Liu

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66537 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823431

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins, forming a liner layer above at least a first upper surface of the first fin and a second upper surface of the second fin, and forming an ion-containing region in the first portion of the liner layer while not forming the ion-containing region in second portion of the liner layer. The method also includes performing a liner etching process so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned above the first fin, and performing at least one etching process to define a reduced-height second fin that is less than an initial first height of the first fin.

Abstract translation: 本文公开的一种说明性方法包括形成第一和第二鳍片，在第一鳍片的至少第一上表面和第二鳍片的第二上表面上方形成衬垫层，并且形成含离子区域 衬垫层的第一部分，而不在衬垫层的第二部分中形成含离子区域。 该方法还包括进行衬里蚀刻工艺，以便去除衬垫层的第二部分，同时使衬垫层的第一部分的至少一部分位于第一散热片之上，并进行至少一个蚀刻工艺以限定 减小高度的第二散热片小于第一散热片的初始第一高度。

公开(公告)号：US20170033178A1

公开(公告)日：2017-02-02

申请号：US14813254

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bharat Krishnan ,  Shishir Ray ,  Jinping Liu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/763 ,  H01L21/02164 ,  H01L21/02345 ,  H01L21/0243 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/76882 ,  H01L21/76883 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

Abstract: Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.

Abstract translation: 提供了集成电路及其制造方法。 根据一个实施例，制造集成电路的方法包括形成由第一材料限定的沟槽。 沟槽填充有第二材料以产生限定在第二材料内的间隙，其中第二材料处于固态。 第二材料在沟槽内回流以减小间隙的体积，然后第二材料在沟槽内固化。

公开(公告)号：US09257519B2

公开(公告)日：2016-02-09

申请号：US14081417

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Joseph F. Shepard, Jr. ,  Keith K. H. Wong

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/336 ,  H01L29/49 ,  H01L29/47 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28202 ,  H01L29/47 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底; 以及栅极结构，其直接设置在所述基板上，所述栅极结构包括：具有不同材料浓度分布的渐变区域; 以及设置在分级区域上的金属层。

公开(公告)号：US20150303295A1

公开(公告)日：2015-10-22

申请号：US14258279

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Xiang Hu ,  Jinping Liu ,  Gabriel Padron Wells ,  Andy Chih-Hung Wei ,  Guillaume Bouche ,  Cuiqin Xu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/51 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings.

Abstract translation: 提供了在半导体器件（例如，FinFET器件）中形成一组接触开口的方法。 具体地，半导体器件包括形成在衬底中的一组翅片，形成在衬底上的栅极结构（例如，替换金属栅极（RMG））以及与栅极结构相邻的一组接触开口，该组接触 具有顶部和底部的开口，其中沿着栅极结构的长度的底部的宽度大于顶部的宽度。 半导体器件还包括形成在该组接触开口内的一组金属触头。

公开(公告)号：US09159794B2

公开(公告)日：2015-10-13

申请号：US14156745

申请日：2014-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jinping Liu

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs.

Abstract translation: 本发明的实施例提供了一种用于finFET的改进的接触形成方法。 在翅片上形成外延半导体区域。 接触蚀刻停止层（CESL）沉积在外延区域上。 氮化物 - 氧化物转换处理将氮化物CESL的一部分转化为氧化物。 使用选择性蚀刻工艺去除氧化物转化的部分，并且沉积与外延区域直接物理接触的填充金属。 在该过程期间，使外延区域的损耗（例如气蚀）最小化，导致finFET的接触改善。

公开(公告)号：US20150214369A1

公开(公告)日：2015-07-30

申请号：US14164934

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody A. Fronheiser ,  Bharat V. Krishnan ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Ajey Poovannummoottil Jacob ,  Jinping Liu

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/167 ,  H01L29/26 ,  H01L29/04 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/26 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.

Abstract translation: 本文公开的一种说明性器件包括在具有晶体结构的半导体衬底中限定的鳍，其中鳍的至少一个侧壁基本上位于衬底的100°结晶方向，位于鳍周围的栅极结构， 侧壁间隔物，其位于栅极结构的相对侧附近，以及外延半导体材料，其围绕位于器件的源极/漏极区域中的最外侧壁间隔物横向外侧的翅片周围形成，其中外延半导体材料具有基本上均匀的厚度 沿翅片的侧壁。

公开(公告)号：US09059218B2

公开(公告)日：2015-06-16

申请号：US14030506

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat Krishnan ,  Jinping Liu ,  Zhao Lun ,  Hui Zhan ,  Bongki Lee

IPC: H01L21/22 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/6681 ,  H01L21/2253 ,  H01L21/2652 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.

Abstract translation: 半导体结构包括设置在有源区上的半导体衬底，有源区和伪栅极结构。 在伪栅极结构和有源区域上设置包括底部氧化物层和顶部氮化物层的牺牲保形层，以在源极和漏极注入期间保护虚拟栅极。 使用诸如n型掺杂剂或p型掺杂剂的掺杂剂注入有源区域，以在有源区域中产生源极区域和漏极区域，之后去除牺牲保形层。