公开(公告)号：US07086600B2

公开(公告)日：2006-08-08

申请号：US10466428

申请日：2001-02-02

申请人： Takahiro Osawa ,  Yoichi Kawata ,  Atsushi Fujishima ,  Tamaki Wada ,  Kenichi Imura

发明人： Takahiro Osawa ,  Yoichi Kawata ,  Atsushi Fujishima ,  Tamaki Wada ,  Kenichi Imura

IPC分类号： G06K19/06 ,  G06K19/00

CPC分类号： G06K19/07732 ,  B29C45/14647 ,  G06K19/077 ,  G06K19/07745 ,  H01L23/04 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/5388 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49158 ,  Y10T29/49222 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A memory card wherein a substrate is affixed to a cap is formed without the projection of substrate edges from a back surface of the cap. The memory card includes a substrate having a sealing member bonded to a recess in the cap. By utilizing a difference in thermal expansion coefficient between the sealing member and the substrate, the substrate is warped so that its central portion projects away from the cap. The shallow recess is deeper than the sum of the thickness of the substrate and the thickness of an adhesive for bonding the substrate to the bottom of the shallow recess, whereby peripheral edges of the substrate retract into the shallow recess without projecting from the back surface of the cap. The cap is shaped as a card several millimeters thick. A memory chip and control chip are incorporated in the sealing member.

摘要翻译： 其中衬底固定在帽上的存储卡被形成，而没有衬底边缘从盖的后表面突出。 存储卡包括具有接合到盖中的凹部的密封构件的基板。 通过利用密封构件和基板之间的热膨胀系数的差异，基板翘曲，使得其中心部分远离盖突出。 浅凹部比基板的厚度和用于将基板粘结到浅凹部的底部的粘合剂的厚度的总和深，从而基板的周边边缘缩回到浅凹部中而不从背面突出 这顶帽子。 盖形成为几毫米厚的卡。 存储芯片和控制芯片被结合在密封构件中。

公开(公告)号：US06552437B1

公开(公告)日：2003-04-22

申请号：US09806950

申请日：2001-04-06

申请人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Tomoko Higashino ,  Takafumi Nishita ,  Hiroshi Ohno

发明人： Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Tomoko Higashino ,  Takafumi Nishita ,  Hiroshi Ohno

IPC分类号： H01L2940

CPC分类号： H01L24/48 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/01026 ,  H01L2224/48227 ,  H01L2924/3512 ,  H01L2924/00012

摘要： Semiconductor chips (4), (5) are bonded and fixed to each other in a state where the rear surfaces of the respective semiconductor chips are faced to each other so that the other longer latus (4A2) of the semiconductor chip (4) and one longer latus (5A1) of the semiconductor chip (5) may confront the side of leads (10B), and supporting leads (8) are bonded and fixed onto the circuit forming surface (4A) of the semiconductor chip (4) or the circuit forming surface (5A) of the semiconductor chip (5). Owing to such a construction, the structure of a semiconductor device can be thinned. The semiconductor chips (4), (5) are bonded and fixed to each other in a state where the, positions of the respective semiconductor chips are staggered relatively to each other so that the electrodes (6) of the semiconductor chip (4) may lie outside the other longer latus (5A2) of the semiconductor chip (5), and that the electrodes (6) of the semiconductor chip (5) may lie outside the other longer latus (4A2) of the semiconductor chip (4). Owing to such a construction, the available percentage of the products of the semiconductor device can be heightened.

摘要翻译： 半导体芯片（4），（5）在各半导体芯片的背面彼此相对的状态下彼此接合固定，使得半导体芯片（4）的另一个较长的凹槽（4A2）和 半导体芯片（5）的一个较长的凹槽（5A1）可以面对引线（10B）的侧面，并且支撑引线（8）被接合并固定到半导体芯片（4）的电路形成表面（4A）上或 半导体芯片（5）的电路形成表面（5A）。 由于这样的结构，半导体器件的结构可以变薄。半导体芯片（4），（5）在各自的半导体芯片的位置相对于每个半导体芯片交错的状态下彼此接合并固定 使得半导体芯片（4）的电极（6）可以位于半导体芯片（5）的另一个较长的凹槽（5A2）之外，并且半导体芯片（5）的电极（6）可以位于外部 半导体芯片（4）的另一个较长的凹槽（4A2）。 由于这样的结构，可以提高半导体器件的产品的可用百分比。

公开(公告)号：US06545349B2

公开(公告)日：2003-04-08

申请号：US09779609

申请日：2001-02-09

申请人： Akihiko Iwaya ,  Tamaki Wada ,  Masachika Masuda

发明人： Akihiko Iwaya ,  Tamaki Wada ,  Masachika Masuda

IPC分类号： H01L2348

CPC分类号： H01L24/06 ,  H01L21/565 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/48647 ,  H01L2224/4866 ,  H01L2224/48699 ,  H01L2224/48747 ,  H01L2224/4876 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85447 ,  H01L2224/8546 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

公开(公告)号：US06531773B2

公开(公告)日：2003-03-11

申请号：US09930942

申请日：2001-08-17

申请人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

发明人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

IPC分类号： H01L2334

CPC分类号： H01L24/49 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01039 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside of the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.

公开(公告)号：US06492727B2

公开(公告)日：2002-12-10

申请号：US09930943

申请日：2001-08-17

申请人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

发明人： Hirotaka Nishizawa ,  Masachika Masuda ,  Kouichi Kanemoto ,  Tamaki Wada

IPC分类号： H01L2334

CPC分类号： H01L24/49 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01039 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside of the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.

公开(公告)号：US06285074B1

公开(公告)日：2001-09-04

申请号：US09761572

申请日：2001-01-18

申请人： Michiaki Sugiyama ,  Tamaki Wada ,  Masachika Masuda

发明人： Michiaki Sugiyama ,  Tamaki Wada ,  Masachika Masuda

IPC分类号： H01L23495

摘要： In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.

公开(公告)号：US6153922A

公开(公告)日：2000-11-28

申请号：US139563

申请日：1998-08-25

申请人： Michiaki Sugiyama ,  Tamaki Wada ,  Masachika Masuda

发明人： Michiaki Sugiyama ,  Tamaki Wada ,  Masachika Masuda

IPC分类号： H01L23/28 ,  H01L21/60 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/4899 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L24/45 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041

摘要： In a package having an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.

摘要翻译： 在具有位于半导体芯片的主面上的内部引线部分布置的LOC（芯片上）结构的封装中，存在用于使封装变薄和加速信号传输的技术。 具体地，通过部分地减小布置在半导体芯片的主面上的信号内引线的厚度，密封树脂的厚度减小，同时确保封装的机械强度。 此外，布置在半导体芯片的主表面上方的信号内引线以与半导体芯片的主表面成预定间隔布置。 供电内引线被连接到半导体芯片的主面，从而提供具有减小的寄生电容的封装。

公开(公告)号：US5895969A

公开(公告)日：1999-04-20

申请号：US960332

申请日：1997-10-29

申请人： Masachika Masuda ,  Tamaki Wada

发明人： Masachika Masuda ,  Tamaki Wada

IPC分类号： H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H01L23/48

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/49506 ,  H01L23/49555 ,  H01L23/49582 ,  H01L25/105 ,  H05K3/3426 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/85439 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/145 ,  H05K1/181 ,  H05K3/3421 ,  Y02P70/613

摘要： Ends of inner leads are disposed in the vicinity of a peripheral end of a semiconductor chip and a portion of an insulating film tape is affixed to a main surface of the semiconductor chip by an adhesive while other portions of the insulating film tape are affixed to portions of the inner leads by an adhesive. Electrode pads provided in the main surface of the semiconductor chip are electrically connected to the ends of the corresponding inner leads by bonding wires, and the semiconductor chip, the inner leads, the electrode pads, the insulating film tape and the bonding wires are sealed by a resin molding. The thickness of the insulating film tape is smaller than a height from the main surface of the semiconductor chip to an apex of the bonding wire. Surfaces of the ends of the inner leads connected to the bonding wires are positioned lower than the main surface of the semiconductor chip and the inner leads are positioned between the main surface and an opposite surface of the semiconductor chip.

摘要翻译： 内引线的端部设置在半导体芯片的周缘附近，绝缘膜带的一部分通过粘合剂固定在半导体芯片的主表面上，绝缘膜带的其它部分固定到部分 的内引线。 设置在半导体芯片的主表面的电极焊盘通过接合线电连接到相应的内引线的端部，半导体芯片，内引线，电极焊盘，绝缘膜带和接合线被 树脂成型。 绝缘膜带的厚度小于从半导体芯片的主表面到接合线的顶点的高度。 连接到接合线的内部引线的端部的表面位于比半导体芯片的主表面低的位置，内部引线位于半导体芯片的主表面和相对表面之间。

公开(公告)号：US20130260461A1

公开(公告)日：2013-10-03

申请号：US13883371

申请日：2011-11-09

申请人： Eiji Kobayashi ,  Tamaki Wada ,  Yasutaka Fujita ,  Norihiro Yoshinaga ,  Masako Doi ,  Yasuhiro Fujimoto ,  Takumi Teratani

发明人： Eiji Kobayashi ,  Tamaki Wada ,  Yasutaka Fujita ,  Norihiro Yoshinaga ,  Masako Doi ,  Yasuhiro Fujimoto ,  Takumi Teratani

IPC分类号： C12N5/071 ,  C08B31/04 ,  C08B37/02 ,  C07H3/04

CPC分类号： C12N5/0667 ,  A01N1/0226 ,  A61K9/0019 ,  A61K35/28 ,  A61K47/26 ,  A61K47/36 ,  C07H3/04 ,  C08B31/04 ,  C08B37/0021 ,  C12N5/0663 ,  C12N2500/34

摘要： The present invention provides a mammalian stem cell suspension containing mammalian stem cells and at least one polysaccharide such as trehalose, and the like; a mammalian stem cell aggregation inhibitor containing polysaccharide such as trehalose, and the like; a method of suppressing aggregation of mammalian stem cells, containing suspending the mammalian stem cells in an aqueous physiological solution containing polysaccharide; an inhibitor of a decrease in the survival rate of mammalian stem cells containing polysaccharide such as trehalose and the like; a method of suppressing a decrease in the survival rate of mammalian stem cells, containing suspending the mammalian stem cells in an aqueous physiological solution containing polysaccharides, and the like.

摘要翻译： 本发明提供了含有哺乳动物干细胞和至少一种多糖如海藻糖等的哺乳动物干细胞悬浮液; 含有海藻糖等多糖的哺乳动物干细胞聚集抑制剂等; 一种抑制哺乳动物干细胞聚集的方法，其包含将哺乳动物干细胞悬浮在含有多糖的生理水溶液中; 是含有海藻糖等多糖的哺乳动物干细胞存活率下降的抑制剂; 抑制哺乳动物干细胞的存活率降低的方法，其包含将哺乳动物干细胞悬浮在含有多糖的生理水溶液等中。

公开(公告)号：US07322531B2

公开(公告)日：2008-01-29

申请号：US11326448

申请日：2006-01-06

申请人： Takahiro Osawa ,  Yoichi Kawata ,  Atsushi Fujishima ,  Tamaki Wada ,  Kenichi Imura

发明人： Takahiro Osawa ,  Yoichi Kawata ,  Atsushi Fujishima ,  Tamaki Wada ,  Kenichi Imura

IPC分类号： G06K19/06 ,  G06K19/00

CPC分类号： G06K19/07732 ,  B29C45/14647 ,  G06K19/077 ,  G06K19/07745 ,  H01L23/04 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/5388 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49158 ,  Y10T29/49222 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A memory card wherein a substrate is affixed to a cap is formed without the projection of substrate edges from a back surface of the cap. The memory card includes a substrate having a sealing member bonded to a recess in the cap. By utilizing a difference in thermal expansion coefficient between the sealing member and the substrate, the substrate is warped so that its central portion projects away from the cap. The shallow recess is deeper than the sum of the thickness of the substrate and the thickness of an adhesive for bonding the substrate to the bottom of the shallow recess, whereby peripheral edges of the substrate retract into the shallow recess without projecting from the back surface of the cap. The cap is shaped as a card several millimeters thick. A memory chip and control chip are incorporated in the sealing member.

摘要翻译： 其中衬底固定在帽上的存储卡被形成，而没有衬底边缘从盖的后表面突出。 存储卡包括具有接合到盖中的凹部的密封构件的基板。 通过利用密封构件和基板之间的热膨胀系数的差异，基板翘曲，使得其中心部分远离盖突出。 浅凹部比基板的厚度和用于将基板粘结到浅凹部的底部的粘合剂的厚度的总和深，从而基板的周边边缘缩回到浅凹部中而不从背面突出 这顶帽子。 盖形成为几毫米厚的卡。 存储芯片和控制芯片被结合在密封构件中。