公开(公告)号：US20170040238A1

公开(公告)日：2017-02-09

申请号：US15296995

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Jiro Kubota ,  Omkar G. Karhade ,  Shawna M. Liff ,  Kinya Ichikawa ,  Nitin A. Deshpande

IPC: H01L23/18 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L25/10

CPC classification number: H01L23/18 ,  H01L21/566 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.

Abstract translation: 微电子封装可以形成有围绕微电子管芯的图框加强件，以减少微电子封装的翘曲。 用于制造这种微电子封装的实施例可以包括形成具有有源表面和相对背面的微电子管芯，其中微电子管芯有源表面可以附接到微电子衬底。 可以形成具有穿过其中的开口的相框加强件并将其放置在脱模膜上，其中模塑材料可以沉积在画框加强件和释放膜上。 微电子管芯可以插入模具材料中，其中微电子管芯的至少一部分延伸到相框开口中。 可以去除剥离膜，然后可以移除在微电子管芯背表面上延伸的一部分模具材料以形成微电子封装。

公开(公告)号：US20160155705A1

公开(公告)日：2016-06-02

申请号：US15004774

申请日：2016-01-22

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Christopher J. Nelson ,  Omkar G. Karhade ,  Feras Eid ,  Nitin A. Deshpande ,  Shawna M. Liff

IPC: H01L23/538 ,  H01L23/367 ,  H01L21/56

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/24145 ,  H01L2224/24245 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/0665

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

公开(公告)号：US20150187727A1

公开(公告)日：2015-07-02

申请号：US14643329

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Chuan Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K1/181 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Abstract translation: 本公开涉及制造微电子封装的领域，其中在沉积在第一基板上的电介质层中形成空腔以保持焊接互连之间的分离。 在一个实施例中，空腔可以具有倾斜的侧壁。 在另一个实施例中，焊膏可以沉积在空腔中，并且在加热时可以形成焊料结构。 在其它实施例中，焊料结构可以放置在空腔中，或者可以形成在可以连接第一衬底的第二衬底上。 在其它实施例中，可以在第一基板和第二基板上形成焊料结构。 焊料结构可以用于通过与第二衬底上的接触焊盘或焊料结构的接触和回流来形成焊料互连。

公开(公告)号：US12300666B2

公开(公告)日：2025-05-13

申请号：US18597684

申请日：2024-03-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Amr Elshazly ,  Arun Chandrasekhar ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US20250112208A1

公开(公告)日：2025-04-03

申请号：US18478686

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Thomas L. Sounart ,  Feras Eid ,  Kimin Jun ,  Tushar Kanti Talukdar ,  Andrey Vyatskikh ,  Johanna Swan ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/15

Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.

公开(公告)号：US20250105053A1

公开(公告)日：2025-03-27

申请号：US18473711

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Han Wui Then ,  Feras Eid ,  James E. Jaussi ,  Ganesh Balamurugan ,  Thomas L. Sounart ,  Johanna Swan ,  Henning Braunisch ,  Tushar Kanti Talukdar ,  Shawna M. Liff

IPC: H01L21/762 ,  G02B6/30 ,  G02B6/43 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, and/or electronic integrated circuits. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

公开(公告)号：US20250105046A1

公开(公告)日：2025-03-27

申请号：US18473905

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Thomas L. Sounart ,  Feras Eid ,  Tushar Kanti Talukdar ,  Brandon M. Rawlings ,  Andrey Vyatskikh ,  Carlos Bedoya Arroyave ,  Kimin Jun ,  Shawna M. Liff ,  Grant M. Kloster ,  Richard F. Vreeland ,  William P. Brezinski ,  Johanna Swan

IPC: H01L21/683 ,  H01L23/00 ,  H01L25/065

Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a layer of integrated circuit (IC) components is received, and a second substrate with one or more adhesive areas is received. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

公开(公告)号：US12142510B2

公开(公告)日：2024-11-12

申请号：US17132429

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Michael J. Baker ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L21/683 ,  H01L21/67 ,  H01L23/00

Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.

公开(公告)号：US12062631B2

公开(公告)日：2024-08-13

申请号：US17025181

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A Elsherbini ,  Krishna Bharath ,  Kevin P. O'Brien ,  Kimin Jun ,  Han Wui Then ,  Mohammad Enamul Kabir ,  Gerald S. Pasdast ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/05147 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09055 ,  H01L2224/09505 ,  H01L2224/29186 ,  H01L2224/32145

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US11984439B2

公开(公告)日：2024-05-14

申请号：US16161578

申请日：2018-10-16

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Shawna M. Liff ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/538 ,  H01L23/66 ,  H01L25/18

CPC classification number: H01L25/18 ,  H01L23/5329 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/0237

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.