公开(公告)号：US20140091446A1

公开(公告)日：2014-04-03

申请号：US13631471

申请日：2012-09-28

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L23/498 ,  H01L23/36 ,  H01L21/56

CPC classification number: H01L23/49861 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49579 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  Y10T29/49121 ,  Y10T29/49172 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract translation: 半导体器件包括具有覆盖铝合金引线框架的暴露部分的钝化层的铝合金引线框架。 由于铝合金是低成本材料，其硬度和柔韧性适用于冲压，弯曲，成型等变形过程，铝合金引线框架适合批量生产; 此外，由于其重量比铜或铁镍材料低得多，因此铝合金引线框对于半导体器件的生产非常方便。

公开(公告)号：US08642397B1

公开(公告)日：2014-02-04

申请号：US13607775

申请日：2012-09-09

Applicant: Yuping Gong ,  Yan Xun Xue ,  Ping Huang

Inventor： Yuping Gong ,  Yan Xun Xue ,  Ping Huang

IPC: H01L21/44

CPC classification number: H01L23/3114 ,  H01L23/3121 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A wafer-level semiconductor package method comprising the step of providing a first wafer comprising a plurality of first dies each having a first, a second and a third electrodes formed on its front surface; attaching a second die having a fourth and a fifth electrodes formed on its front surface and a sixth electrode formed at its back surface onto each of the first die of the first wafer with the sixth electrode at the back surface of the second die attached and electrically connected to the second electrode at the front surface of the first die; and cutting the first wafer to singulate individual semiconductor packages.

Abstract translation: 一种晶片级半导体封装方法，包括提供包括多个第一裸片的第一晶片的步骤，所述第一晶片具有形成在其前表面上的第一，第二和第三电极; 将具有在其前表面上形成的第四和第五电极的第二管芯和在其后表面上形成的第六电极连接到第一晶片的每个第一管芯上，第二电极的后表面上的第六电极被附接并电连接 在第一模具的前表面处连接到第二电极; 并切割第一晶片以单独的半导体封装。

公开(公告)号：US08450152B2

公开(公告)日：2013-05-28

申请号：US13193474

申请日：2011-07-28

Applicant: Yuping Gong ,  Yan Xun Xue

Inventor： Yuping Gong ,  Yan Xun Xue

IPC: H01L21/00

CPC classification number: H01L23/49537 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49562 ,  H01L23/49568 ,  H01L2224/16245 ,  H01L2224/32245

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.

Abstract translation: 双面露出的半导体器件包括安装在导热但不导电的第二引线框架的顶部的导电第一引线框架和翻转并附接在第一引线框架顶部上的半导体芯片。 翻转芯片顶部的栅极和源极电极分别与第一引线框架的栅极和源极引脚形成电连接。 第一和第二引线框架的翻转芯片和中心部分然后用模塑料封装，使得形成在第二引线框架的中心处的散热器和在半导体芯片的底部的漏电极暴露在两个相对的 半导体器件的侧面。 因此，在不增加半导体器件的尺寸的情况下，有效地提高了半导体器件的散热性能。

公开(公告)号：US20130037917A1

公开(公告)日：2013-02-14

申请号：US13602144

申请日：2012-09-01

Applicant: Yan Xun Xue

Inventor： Yan Xun Xue

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/32245 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.

Abstract translation: 一种形成具有厚底金属的晶片级芯片级（WLCS）封装器件的方法，包括将包括多个厚底金属的引线框架附接到半导体晶片的背金属层上的步骤，该半导体晶片包括多个半导体芯片， 形成在每个芯片的前表面上的多个接合焊盘，每个厚的底部金属与每个芯片的中心部分对准; 沿着划线形成多个后侧切割槽并填充有封装材料，从而切割包装材料从而形成多个单个WLCS封装装置。

公开(公告)号：US08338232B2

公开(公告)日：2012-12-25

申请号：US13045407

申请日：2011-03-10

Applicant: Lei Shi ,  Yan Xun Xue ,  Yuping Gong

Inventor： Lei Shi ,  Yan Xun Xue ,  Yuping Gong

IPC: H01L21/56

CPC classification number: H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2224/83

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract translation: 公开了专门用于倒装芯片垂直功率器件的封装半导体器件的制备方法。 在这些方法中，将垂直半导体芯片倒装芯片连接到引线框架，然后用塑料包装材料封装。 然后将封装的芯片变薄到预定厚度。 通过蚀刻至少连接的引线框架的底部部分，形成连接芯片与外部电路的接触端子。

公开(公告)号：US20120025298A1

公开(公告)日：2012-02-02

申请号：US12846743

申请日：2010-07-29

Applicant: Yueh-Se Ho ,  Yan Xun Xue

Inventor： Yueh-Se Ho ,  Yan Xun Xue

IPC: H01L29/78 ,  H01L21/302

CPC classification number: H01L23/485 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/03 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Abstract translation: 描述半导体器件，制造半导体器件的方法和电路封装组件。 半导体器件可以具有带有第一和第二表面的半导体衬底和它们之间的侧壁。 第一和第二表面上的第一和第二导电焊盘与衬底中对应的第一和第二半导体器件结构电接触。 第一表面和侧壁上的绝缘体层覆盖第一表面上的第一导电焊盘的一部分。 在第一导电焊盘和侧壁上的绝缘体层的一部分上的导电层与第二导电焊盘电接触。 绝缘体层防止导电层在第一和第二导电焊盘之间形成电接触。

公开(公告)号：US20160056098A9

公开(公告)日：2016-02-25

申请号：US14204019

申请日：2014-03-11

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H01L23/49582 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49861 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83486 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/013 ,  H01L2924/05432 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

公开(公告)号：US09224669B2

公开(公告)日：2015-12-29

申请号：US14097433

申请日：2013-12-05

Applicant: Yan Xun Xue

Inventor： Yan Xun Xue

IPC: H01L21/00 ,  H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/304 ,  H01L21/56

CPC classification number: H01L23/535 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05025 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract translation: 一种用于提供具有增加的接触焊盘区域的晶片级封装的方法，包括以下步骤：在晶片顶表面上形成第一封装层，研磨晶片背面并蚀刻通孔，沉积金属以填充通孔并覆盖晶片背面， 从晶片背面切割晶片，形成分开每个芯片的多个沟槽，然后沉积填充沟槽并覆盖晶片背面金属的第二封装层，减小第一封装层厚度以露出填充凹槽的第二封装层并形成多个 接触垫重叠在第一包装层上，然后切割槽中的第二包装层以形成单个包装。

公开(公告)号：US20150262925A1

公开(公告)日：2015-09-17

申请号：US14204019

申请日：2014-03-11

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H01L23/49582 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49861 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83486 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/013 ,  H01L2924/05432 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract translation: 半导体器件包括具有覆盖铝合金引线框架的暴露部分的钝化层的铝合金引线框架。 由于铝合金是低成本材料，其硬度和柔韧性适用于冲压，弯曲，成型等变形过程，铝合金引线框架适合批量生产; 此外，由于其重量比铜或铁镍材料低得多，因此铝合金引线框对于半导体器件的生产非常方便。

公开(公告)号：US09136379B2

公开(公告)日：2015-09-15

申请号：US13871144

申请日：2013-04-26

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/42372 ,  H01L29/781 ,  H01L2224/04105 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

Abstract translation: 底部源极功率金属氧化物半导体场效应晶体管（MOSFET）器件包括形成在半导体芯片的第一表面上的初始绝缘层上的栅电极和源电极，以及形成在半导体芯片的第二表面上的漏电极 半导体芯片 源电极包括源极金属，形成在源极金属上的源极电极凸点和源极电极凸起顶部上的源电极金属层。 第一绝缘层覆盖栅电极。 从芯片的第二表面形成与栅电极对准的贯通孔，以将栅电极的一部分从第二表面露出。