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    METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE
    91.
    发明申请
    METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE 审中-公开
    通过STUB共鸣减少的方法和系统

    公开(公告)号：US20090049414A1

    公开(公告)日：2009-02-19

    申请号：US11840075

    申请日：2007-08-16

    Applicant: Bhyrav M. MUTNURY ,  Moises Cases ,  Wallace G. Tuten ,  Erdem Matoglu

    Inventor： Bhyrav M. MUTNURY ,  Moises Cases ,  Wallace G. Tuten ,  Erdem Matoglu

    IPC: G06F17/50 ,  H05K1/11

    CPC classification number: H05K3/0005 ,  G06F17/5068 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09636

    Abstract: Reducing via stub resonance in printed circuit boards. In one aspect, a method for reducing via stub resonance in a circuit board includes determining that resonance exists for a signal to be transmitted through a signal via extending across a plurality of layers in the circuit board. The resonance is caused by a via stub of the signal via, the via stub extending past a layer connected to the signal via. A location is determined for a ground via to be placed relative to the signal via, the location of the ground via being determined based on reducing the resonance for the signal to be transmitted in the signal via.

    Abstract translation: 通过印刷电路板中的短截线减少。 在一个方面，一种用于减少电路板中的通路短路谐振的方法包括确定通过延伸穿过电路板中的多个层的通过信号传输的信号的共振。 谐振是由信号通孔的通孔短路引起的，通孔短路延伸通过与信号通孔连接的层。 确定相对于信号通路放置的地面通路的位置，基于通过减少在信号通道中要发送的信号的谐振来确定地面的位置。

    High-speed router with backplane using tuned-impedance thru-holes and vias
    93.
    发明授权
    High-speed router with backplane using tuned-impedance thru-holes and vias 有权
    具有背板的高速路由器使用调谐阻抗通孔和通孔

    公开(公告)号：US07336502B1

    公开(公告)日：2008-02-26

    申请号：US10454735

    申请日：2003-06-03

    Applicant: Joel R. Goergen

    Inventor： Joel R. Goergen

    IPC: H01R12/16

    CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09781

    Abstract: A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. Specific via designs reduce differential signal distortion due to the via pair, allowing the backplane to operate reliably at differential signal rates in excess of 3 Gigabits per second. In particular, each via passes through nonfunctional conductive pads on selected digital ground plane layers, the pads separated from the remainder of its ground plane layer by a clearance, thereby modifying the impedance of the via and reducing reflections from the stubs created by the via.

    Abstract translation: 公开了一种高速路由器背板。 路由器背板在多个信号层上使用差分信号对，每个信号对夹在一对数字接地层之间。 为了降低路由复杂度，差分信号对中的至少一些在其路径的某处沿着不同的信号层路由通路对。 特定的通孔设计可减少由于通孔对导致的差分信号失真，从而允许背板在差分信号速率下可靠地运行，每秒超过3千兆位。 特别地，每个通孔通过选定的数字接地平面层上的非功能导电焊盘，焊盘与其接地平面层的其余部分间隔一定距离，从而修改通孔的阻抗并减少由通孔产生的短截线的反射。

    Semiconductor package substrate
    94.
    发明申请
    Semiconductor package substrate 有权
    半导体封装基板

    公开(公告)号：US20070273026A1

    公开(公告)日：2007-11-29

    申请号：US11701767

    申请日：2007-02-02

    Applicant: Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    Inventor： Hsieh-Tsung Tien ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    IPC: H01L23/488

    CPC classification number: H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

    Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

    Abstract translation: 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

    Method and structure for implementing enhanced differential signal trace routing
    97.
    发明申请
    Method and structure for implementing enhanced differential signal trace routing 审中-公开
    实现增强差分信号跟踪路由的方法和结构

    公开(公告)号：US20040189418A1

    公开(公告)日：2004-09-30

    申请号：US10401257

    申请日：2003-03-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Gerald Keith Bartley ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew B. Maki ,  Mark Owen Maxson

    IPC: H05K007/02 ,  H01P003/02

    CPC classification number: H05K1/0245 ,  H01P3/08 ,  H05K1/115 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718

    Abstract: A method and structure are provided for implementing enhanced differential signal trace routing in a printed circuit board. The structure includes a differential signal trace pair and a differential pair via arrangement including a pair of vias. The pair of vias is coupled to the differential signal trace pair for routing the differential signal trace pair between first and second layers of the PCB. The vias are laterally offset by a predefined spacing sharing overlapping clearance holes and are diagonally oriented to allow minimal separation of the differential signal trace pair and matched signal trace lengths of the differential signal trace pair.

    Abstract translation: 提供了一种用于在印刷电路板中实现增强的差分信号迹线路由的方法和结构。 该结构包括差分信号迹线对和包括一对通孔的差分对通孔装置。 该对通孔耦合到差分信号迹线对，用于在PCB的第一和第二层之间路由差分信号迹线对。 通孔横向偏移共享重叠间隙孔的预定间隔，并且对角线定向以允许微分信号轨迹对和差分信号轨迹对的匹配信号迹线长度的最小间隔。

    Quadrax to twinax conversion apparatus and method
    98.
    发明授权
    Quadrax to twinax conversion apparatus and method 有权
    Quadrax到twinax转换装置和方法

    公开(公告)号：US06794578B2

    公开(公告)日：2004-09-21

    申请号：US10096087

    申请日：2002-03-11

    Applicant: Salvatore Bracaleone

    Inventor： Salvatore Bracaleone

    IPC: H01B708

    CPC classification number: H05K1/0245 ,  H01R12/523 ,  H01R13/622 ,  H01R13/746 ,  H01R24/44 ,  H01R24/542 ,  H01R24/56 ,  H01R25/003 ,  H01R2103/00 ,  H01R2107/00 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09636 ,  H05K2201/10356

    Abstract: A Quadrax to Twinax conversion apparatus includes stacked trace layers of transmission line with a ground plane between the trace layers. Embodiments include trace layers of stripline or microstrip. Orthogonal plated through holes include a diagonal pair of through holes in electrical contact with traces on one of the trace layers and another diagonal pair of through holes in electrical contact with another trace layer. Contact pins extend through these orthogonal plated through holes with one pair of pins making electrical contact with one trace layer and the other pair of pins making electrical contact with another trace layer. The conversion apparatus electrically connects Twinax cables to respectively different trace layers without crossing over or disturbing the relative positions of the Quadrax diagonal pairs for very efficient high-speed data transfer from four wire Quadrax to two wire Twinax cables.

    Abstract translation: Quadrax至Twinax转换装置包括在迹线层之间具有接地平面的传输线的堆叠迹线层。 实施例包括带状线或微带的迹线层。 正交电镀通孔包括与其中一个迹线层上的迹线电接触的对角对对的通孔，以及与另一个迹线层电接触的另一对角线对通孔。 接触销通过这些正交电镀通孔延伸，一对引脚与一个迹线层电接触，另一对引脚与另一个迹线层电接触。 转换装置将Twinax电缆电连接到不同的迹线层，而不会跨越或干扰Quadrax对角线对的相对位置，从而从四线Quadrax到两线双绞线电缆进行非常有效的高速数据传输。

    High-speed router with single backplane distributing both power and signaling
    99.
    发明申请
    High-speed router with single backplane distributing both power and signaling 有权
    具有单个背板的高速路由器分配电源和信令

    公开(公告)号：US20030179741A1

    公开(公告)日：2003-09-25

    申请号：US10068418

    申请日：2002-02-05

    Applicant: Force 10 Networks, Inc.

    Inventor： Joel R. Goergen

    IPC: G06F013/00

    CPC classification number: H05K1/0245 ,  H04Q1/03 ,  H04Q1/10 ,  H04Q1/155 ,  H04Q2201/12 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09354 ,  H05K2201/09636

    Abstract: A high-speed, high-power modular router is disclosed. As opposed to conventional designs using optical backplane signaling and/or bus bars for power distribution, the disclosed embodiments combine high-power, low-noise power distribution with high-speed signal routing in a common backplane. Disclosed backplane features allow backplane signaling at 2.5 Gbps or greater on electrical differential pairs distributed on multiple high-speed signaling layers. Relatively thick power distribution layers are embedded within the backplane, shielded from the high-speed signaling layers by digital ground layers and other shielding features. A router using such a backplane provides a level of performance and economy that is believed to be unattainable by the prior art.

    Abstract translation: 公开了一种高速大功率模块化路由器。 与使用光背板信号和/或用于功率分配的汇流条的常规设计相反，所公开的实施例将大功率，低噪声功率分配与公共背板中的高速信号路由相结合。 公开的背板特征允许在分布在多个高速信令层上的电差分对上以2.5Gbps或更大的背板信号。 相对厚的配电层嵌入在背板内，通过数字接地层和其他屏蔽特性与高速信号层屏蔽。 使用这种背板的路由器提供了一种被认为是现有技术无法实现的性能和经济性。

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