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    Protocol For Refresh Between A Memory Controller And A Memory Device
    102.
    发明公开
    Protocol For Refresh Between A Memory Controller And A Memory Device 审中-公开

    公开(公告)号：US20230223067A1

    公开(公告)日：2023-07-13

    申请号：US18078934

    申请日：2022-12-10

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/40615 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/00 ,  G11C2211/4067

    Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

    Offset calibration for successive approximation register analog to digital converter
    106.
    发明授权
    Offset calibration for successive approximation register analog to digital converter 有权

    公开(公告)号：US11671108B2

    公开(公告)日：2023-06-06

    申请号：US17728607

    申请日：2022-04-25

    Applicant: Rambus Inc.

    Inventor： Kenneth C. Dyer ,  Marcus Van Ierssel

    IPC: H03M1/10 ,  H03M1/06 ,  H03M1/46

    CPC classification number: H03M1/1023 ,  H03M1/0639 ,  H03M1/46

    Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.

    REDUNDANT DATA LOG RETRIEVAL IN MULTI-PROCESSOR DEVICE
    108.
    发明公开
    REDUNDANT DATA LOG RETRIEVAL IN MULTI-PROCESSOR DEVICE 审中-公开

    公开(公告)号：US20230161599A1

    公开(公告)日：2023-05-25

    申请号：US17968488

    申请日：2022-10-18

    Applicant: Rambus Inc.

    Inventor： Evan Lawrence Erickson

    IPC: G06F9/4401 ,  H04L67/141

    CPC classification number: G06F9/4406 ,  H04L67/141

    Abstract: A device includes interface circuitry to receive requests from at least one host system, a primary processor coupled to the interface circuitry, and a secure processor coupled to the primary processor. In response to a failure of the primary processor, the secure processor is to: verify a log retrieval command received via the interface circuitry, wherein the log retrieval command is cryptographically signed; in response to the verification, retrieve crash dump data stored in memory that is accessible by the primary processor; generate a log file that comprises the retrieved crash dump data; and cause the log file to be transmitted to the at least one host system over a sideband link that is coupled externally to the interface circuitry.

    Cache Memory That Supports Tagless Addressing
    109.
    发明公开
    Cache Memory That Supports Tagless Addressing 审中-公开

    公开(公告)号：US20230153251A1

    公开(公告)日：2023-05-18

    申请号：US17992443

    申请日：2022-11-22

    Applicant: Rambus Inc.

    Inventor： Hongzhong Zheng ,  Trung A. Diep

    IPC: G06F12/1045 ,  G06F12/0802 ,  G06F12/1009

    CPC classification number: G06F12/1063 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1054

    Abstract: The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

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