公开(公告)号：US20110074014A1

公开(公告)日：2011-03-31

申请号：US12567033

申请日：2009-09-25

Applicant: Reza A. Pagaila ,  Yaojian Lin

Inventor： Reza A. Pagaila ,  Yaojian Lin

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/68 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.

Abstract translation: 半导体器件通过提供临时载体并提供具有在其有源表面上形成的多个凸起的半导体管芯制成。 粘合剂材料作为半导体管芯的载体或有源表面上的多个岛或凸起沉积。 粘合剂层也可以作为连续层沉积在模具的载体或活性表面上。 半导体管芯安装在载体上。 密封剂沉积在模具和载体上。 粘合剂材料在沉积密封剂的同时将半导体管芯保持在载体上。 在模具的有效表面上形成互连结构。 互连结构电连接到半导体管芯的凸点。 可以在形成互连结构之前去除粘合剂材料，或者可以在粘合剂材料上形成互连结构。

公开(公告)号：US20110068459A1

公开(公告)日：2011-03-24

申请号：US12714190

申请日：2010-02-26

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo ,  HeeJo Chi

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo ,  HeeJo Chi

IPC: H01L23/52 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

Abstract translation: 半导体器件具有安装在载体上的插入器。 插入器包括在安装到载体之前或之后形成的TSV。 在插入器中形成开口。 插入器可以具有通过第一阶梯部分的第一垂直传导路径和穿过第二阶梯部分的第二垂直传导路径的两级台阶部分。 第一和第二半导体管芯安装在插入件上。 第二管芯设置在插入件的开口内。 分立半导体部件可以安装在插入器上。 可以通过第二管芯或密封剂形成导电通孔。 密封剂沉积在第一和第二管芯和插入件上。 插入器的一部分可以被去除，使得密封剂围绕半导体器件的一侧形成。 互连结构形成在插入件和第二管芯上。

公开(公告)号：US07859085B2

公开(公告)日：2010-12-28

申请号：US12627884

申请日：2009-11-30

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Yaojian Lin

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Yaojian Lin

IPC: H01L29/40 ,  H01L21/44

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L24/19 ,  H01L24/82 ,  H01L24/97 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00012

Abstract: A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via.

Abstract translation: 半导体管芯具有设置在管芯周围的第一绝缘材料。 去除第一绝缘材料的一部分以形成通孔（THV）。 导电材料沉积在THV中。 在模具的有效表面上形成第二绝缘层。 第一无源电路元件形成在第二绝缘层上。 第一个无源通孔形成在THV上。 第一个无源通孔与THV中的导电材料电连接。 第一无源电路元件电连接到第一无源通孔。 在第一无源电路元件上形成第三绝缘层。 在第三绝缘层上形成第二无源电路元件。 在第二无源电路元件上形成第四绝缘层。 多个半导体管芯通过导电通孔堆叠并电连接。

公开(公告)号：US20100270661A1

公开(公告)日：2010-10-28

申请号：US12830390

申请日：2010-07-05

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Yaojian Lin ,  Rui Huang

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Yaojian Lin ,  Rui Huang

IPC: H01L23/52

CPC classification number: H01L23/3128 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/48 ,  H01L25/165 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has an IPD structure formed over a substrate. First and second electrical devices are mounted to a first surface of the IPD structure. An encapsulant is deposited over the first and second electrical devices and IPD structure. A shielding layer is formed over the encapsulant and electrically connected to a conductive channel in the IPD structure. The conductive channel is connected to ground potential to isolate the first and second electrical devices from external interference. A recess can be formed in the encapsulant material between the first and second electrical devices. The shielding layer extends into the recess. An interconnect structure is formed on a second surface of the IPD structure. The interconnect structure is electrically connected to the first and second electrical devices and IPD structure. A shielding cage can be formed over the first electrical device prior to depositing encapsulant.

Abstract translation: 半导体器件具有在衬底上形成的IPD结构。 第一和第二电气装置安装在IPD结构的第一表面上。 密封剂沉积在第一和第二电气设备和IPD结构上。 屏蔽层形成在密封剂之上并电连接到IPD结构中的导电通道。 导电通道连接到地电位，以隔离第一和第二电气装置与外部干扰。 可以在第一和第二电气装置之间的密封剂材料中形成凹部。 屏蔽层延伸到凹槽中。 互连结构形成在IPD结构的第二表面上。 互连结构电连接到第一和第二电气设备和IPD结构。 在沉积密封剂之前，可以在第一电气装置上形成屏蔽笼。

公开(公告)号：US20100270549A1

公开(公告)日：2010-10-28

申请号：US12831047

申请日：2010-07-06

Applicant: Robert C. Frye ,  Yaojian Lin ,  Rui Huang

Inventor： Robert C. Frye ,  Yaojian Lin ,  Rui Huang

IPC: H01L23/60 ,  H01L29/12 ,  H01L29/02 ,  H01L23/52

CPC classification number: H01L27/0248 ,  H01L23/60 ,  H01L23/64 ,  H01L27/016 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/09701 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has an integrated passive device (IPD) formed over a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed over the first side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed over the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed over the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed over the substrate and electrically connects the conductive layer to a ground point.

Abstract translation: 半导体器件具有在衬底上形成的集成无源器件（IPD）。 IPD可以是金属 - 绝缘体 - 金属电容器或形成为线圈导电层的电感器。 在衬底的第一侧或背面上形成信号互连结构。 信号互连结构电连接到IPD。 作为静电放电（ESD）保护结构的一部分，在衬底上形成薄膜ZnO层。 薄膜ZnO层具有作为施加到该层的电压的函数的非线性电阻。 导电层形成在衬底上。 薄膜ZnO层电连接在信号互连结构和导电层之间，以提供ESD路径以保护IPD免受ESD瞬变。 在衬底上形成接地互连结构，并将导电层电连接到接地点。

公开(公告)号：US07799602B2

公开(公告)日：2010-09-21

申请号：US12332277

申请日：2008-12-10

Applicant: Reza A. Pagaila ,  Rui Huang ,  Yaojian Lin

Inventor： Reza A. Pagaila ,  Rui Huang ,  Yaojian Lin

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made by forming a build-up interconnect structure over a substrate. A semiconductor die is mounted to the build-up interconnect structure. The semiconductor die is electrically connected to the build-up interconnect structure. A ground pad is formed on the build-up interconnect structure. An encapsulant is formed over the semiconductor die and build-up interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the build-up interconnect structure to isolate the semiconductor die from inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. The substrate is removed. A backside interconnect structure is formed over the build-up interconnect structure, opposite the semiconductor die.

Abstract translation: 通过在衬底上形成积聚互连结构来制造半导体器件。 半导体管芯安装到堆积互连结构。 半导体管芯与积层互连结构电连接。 在积层互连结构上形成接地焊盘。 在半导体管芯和堆积互连结构之上形成密封剂。 在形成密封剂之前，可以在半导体管芯上方形成屏蔽笼。 在形成积层互连结构之后，在密封剂上形成屏蔽层，以将半导体管芯与器件间干扰隔离。 屏蔽层符合密封剂的几何形状并且电连接到接地垫。 屏蔽层可以通过导电柱电连接到地面。 去除衬底。 在积层互连结构上形成背面互连结构，与半导体管芯相对。

公开(公告)号：US07772081B2

公开(公告)日：2010-08-10

申请号：US12212524

申请日：2008-09-17

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L21/20 ,  H01L29/00

CPC classification number: H01L27/016 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a surface of the IPD by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the resistive and dielectric layers. The first metal layer and the resistive layer are electrically connected to form a resistor and the first metal layer forms a first inductor. A wafer supporter is mounted over the IPD using an adhesive material and a third metal layer is deposited over the IPD. The third metal layer forms a second inductor that is electrically connected to the capacitor and the resistor by the TSVs of the IPD. An interconnect structure is connected to the IPD.

Abstract translation: 通过提供集成无源器件（IPD）制造半导体器件。 在IPD中形成了硅通孔（TSV）。 通过在IPD上沉积第一金属层，在第一金属层上沉积电阻层，在第一金属层上沉积电介质层，并在第一金属层上沉积第二金属层，并在第一金属层的上方沉积第二金属层， 电介质层。 第一金属层和电阻层电连接以形成电阻器，并且第一金属层形成第一电感器。 使用粘合剂材料将晶片支撑件安装在IPD上，并且第三金属层沉积在IPD上。 第三金属层形成第二电感器，其通过IPD的TSV电连接到电容器和电阻器。 互连结构连接到IPD。

公开(公告)号：US07772080B2

公开(公告)日：2010-08-10

申请号：US12167146

申请日：2008-07-02

Applicant: Robert C. Frye ,  Yaojian Lin ,  Rui Huang

Inventor： Robert C. Frye ,  Yaojian Lin ,  Rui Huang

IPC: H01L21/00

CPC classification number: H01L27/0248 ,  H01L23/60 ,  H01L23/64 ,  H01L27/016 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/09701 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has an integrated passive device (IPD) formed on a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed on the front side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed on the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed on the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed on the substrate and electrically connects the conductive layer to a ground point.

Abstract translation: 半导体器件具有形成在衬底上的集成无源器件（IPD）。 IPD可以是金属 - 绝缘体 - 金属电容器或形成为线圈导电层的电感器。 信号互连结构形成在基板的正面或背面。 信号互连结构电连接到IPD。 作为静电放电（ESD）保护结构的一部分，在衬底上形成薄膜ZnO层。 薄膜ZnO层具有作为施加到该层的电压的函数的非线性电阻。 在基板上形成导电层。 薄膜ZnO层电连接在信号互连结构和导电层之间，以提供ESD路径以保护IPD免受ESD瞬变。 在基板上形成接地互连结构，并将导电层电连接到接地点。

公开(公告)号：US07759212B2

公开(公告)日：2010-07-20

申请号：US11964529

申请日：2007-12-26

Applicant: Yaojian Lin ,  Robert C. Frye

Inventor： Yaojian Lin ,  Robert C. Frye

IPC: H01L21/20

CPC classification number: H01L23/52 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/64 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K3/20 ,  H05K3/284 ,  H05K3/4644 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a semiconductor device involves providing a substrate, forming a first passivation layer over the substrate, and forming an integrated passive circuit over the substrate. The integrated passive circuit can include inductors, capacitors, and resistors. A second passivation layer is formed over the integrated passive circuit. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive circuit. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive circuit. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Abstract translation: 制造半导体器件的方法包括提供衬底，在衬底上形成第一钝化层，以及在衬底上形成集成的无源电路。 集成无源电路可以包括电感器，电容器和电阻器。 在集成无源电路上形成第二钝化层。 系统组件被安装到第二钝化层并电连接到第二导电层。 在集成无源电路上形成模具化合物。 模具化合物的热膨胀系数近似等于系统组分的热膨胀系数。 去除衬底。 蚀刻入第一钝化层的开口并且在第一钝化层中的开口上沉积焊料凸块以电连接到集成无源电路。 可以在模制化合物或第一钝化层上形成金属层以进行屏蔽。

公开(公告)号：US20100148360A1

公开(公告)日：2010-06-17

申请号：US12572590

申请日：2009-10-02

Applicant: Yaojian Lin ,  Xusheng Bao ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Xusheng Bao ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/498

CPC classification number: H01L23/5386 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.

Abstract translation: 通过在载体上形成第一导电层制成半导体器件。 第一导电层具有与第一导电层的第二区域电隔离的第一区域。 在第一导电层的第一区域上形成导电柱。 半导体管芯或部件安装到第一导电层的第二区域。 第一密封剂沉积在半导体管芯上并且围绕导电柱。 在第一密封剂上形成第一互连结构。 第一互连结构电连接到导电柱。 载体被移除。 去除第一导电层的一部分。 第一导电层的剩余部分包括互连线和UBM垫。 在第一导电层的剩余部分上形成第二互连结构被去除。