公开(公告)号：US08643148B2

公开(公告)日：2014-02-04

申请号：US13397204

申请日：2012-02-15

Applicant: Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

Inventor： Jing-Cheng Lin ,  Hsin Chang ,  Shih Ting Lin

IPC: H01L21/78

CPC classification number: H01L23/28 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

Abstract translation: 包装部件包括基板，其中基板具有前表面和在前表面上的后表面。 通孔穿过基底。 导电特征设置在衬底的背表面上并电连接到通孔。 第一电介质图案形成导电特征的环覆盖边缘部分。 底部金属（UBM）被布置在导电特征的中心部分上并与其接触。 聚合物接触衬底的侧壁。 将第二电介质图案设置在聚合物上并对准聚合物。 第一和第二电介质图案由相同的电介质材料形成，并且设置在基本上相同的水平。

公开(公告)号：US20130244346A1

公开(公告)日：2013-09-19

申请号：US13420383

申请日：2012-03-14

Applicant: Chien Rhone Wang ,  Chih-Wei Lai ,  Chih-Chiang Chang ,  Kewei Zuo ,  Jing-Cheng Lin

Inventor： Chien Rhone Wang ,  Chih-Wei Lai ,  Chih-Chiang Chang ,  Kewei Zuo ,  Jing-Cheng Lin

IPC: H01L21/66 ,  G06F17/00

CPC classification number: G06F17/00 ,  H01L22/12 ,  H01L22/20 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.

Abstract translation: 公开了包装方法，材料分配方法和装置以及自动测量系统。 在一个实施例中，包装半导体器件的方法包括将第二管芯耦合到第一管芯的顶表面，在第一管芯和第二管芯之间分配第一量的底部填充材料，以及捕获底部填充材料的图像。 基于所捕获的图像，在第一模具和第二模具之间分配第二量或不需要额外量的底部填充材料。

公开(公告)号：US20130233601A1

公开(公告)日：2013-09-12

申请号：US13412958

申请日：2012-03-06

Applicant: Chin-Fu KAO ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

Inventor： Chin-Fu KAO ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H01L24/14 ,  H01L22/32 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14515 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

Abstract: A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps.

Abstract translation: 用于基板的表面金属布线结构包括由第一金属形成的一个或多个功能性微片和由用于接收电测试探针的第二金属形成的电测试焊盘，并电连接到所述一个或多个功能性微波。 表面金属布线结构还包括多个由第一金属形成的牺牲片，其电连接到电测试焊盘，其中牺牲微片比一个或多个功能性微片更靠近电测试垫定位。

公开(公告)号：US20130203215A1

公开(公告)日：2013-08-08

申请号：US13369083

申请日：2012-02-08

Applicant: Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L21/56

CPC classification number: H01L24/97 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/11 ,  H01L24/19 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.

公开(公告)号：US20130187258A1

公开(公告)日：2013-07-25

申请号：US13356173

申请日：2012-01-23

Applicant: Szu Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

Inventor： Szu Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

IPC: H01L27/06 ,  H01L21/78

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11464 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

Abstract translation: 一种方法包括将第一和第二包装部件接合在第三包装部件的顶表面上，并分配聚合物。 聚合物包括在第一和第三包装部件之间的空间中的第一部分，在第二和第三包装部件之间的空间中的第二部分和第一和第二包装部件之间的间隙中的第三部分。 然后在聚合物上进行固化步骤。 在固化步骤之后，将聚合物的第三部分锯切以在第一和第二包装部件之间形成沟槽。

公开(公告)号：US20130119382A1

公开(公告)日：2013-05-16

申请号：US13297845

申请日：2011-11-16

Applicant: Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/544 ,  H01L21/28

CPC classification number: H01L22/32

Abstract: A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed.

Abstract translation: 提供了一种用于电镀触点的系统和方法。 一个实施例包括在触点和测试垫上形成保护层，然后在触头上选择性地去除保护层，而不需要在测试垫上移除保护层。 在保护层仍在测试焊盘上的情况下，可以将导电层电镀到触点上，而不将其覆盖在测试焊盘上。 接触电镀后，触点上的保护层可以被去除。

公开(公告)号：US20130077272A1

公开(公告)日：2013-03-28

申请号：US13247659

申请日：2011-09-28

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H05K7/02 ,  H05K1/09

CPC classification number: H01L22/32 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/13578 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A work piece includes a first copper-containing pillar having a top surface and sidewalls, and a first protection layer on the sidewalls, and not over the top surface, of the first copper-containing pillar. A test pad includes a second copper-containing pillar having a top surface and sidewalls. The test pad is electrically coupled to the first copper-containing pillar. A second protection layer is disposed on the sidewalls, and not over the top surface, of the second copper-containing pillar. The first and the second protection layers include a compound of copper and a polymer, and are dielectric layers.

Abstract translation: 工件包括具有顶表面和侧壁的第一含铜柱，以及第一含铜柱的侧壁而不是顶表面上的第一保护层。 测试垫包括具有顶表面和侧壁的第二含铜柱。 测试垫电耦合到第一含铜柱。 第二保护层设置在第二含铜柱的侧壁上，而不是在顶表面上。 第一和第二保护层包括铜和聚合物的化合物，并且是电介质层。

公开(公告)号：US08199540B2

公开(公告)日：2012-06-12

申请号：US12683412

申请日：2010-01-06

Applicant: Ching-Shan Leu ,  Jing-Cheng Lin ,  Shun-Yuan Wu

Inventor： Ching-Shan Leu ,  Jing-Cheng Lin ,  Shun-Yuan Wu

IPC: H02J1/10 ,  H02J3/14 ,  H02M7/08 ,  H02M7/10

CPC classification number: H02M3/155 ,  H02M3/158 ,  H02M2001/009 ,  Y10T307/406

Abstract: A high voltage gain power converter includes: a main switch element; an assistant switch element; a first inductive element, a first switch element, and a first capacitive element; and a second inductive element, a second switch element, and a second capacitive element. The first inductive element is connected between an input node and first switch element. The first capacitive element, connected between the first switch element and ground, provides a first boost output voltage. The second inductive element is connected between the main switch element and first capacitive element. The second switch element is connected to a common node of the second inductive element and main switch element. The second capacitive element, connecting the second switch element to a first node, provides a second boost output voltage. The assistant switch element is connected between the first inductive element and common node of the second inductive element and main switch element.

Abstract translation: 高压增益功率转换器包括：主开关元件; 辅助开关元件; 第一电感元件，第一开关元件和第一电容元件; 以及第二感应元件，第二开关元件和第二电容元件。 第一电感元件连接在输入节点和第一开关元件之间。 连接在第一开关元件和地之间的第一电容元件提供第一升压输出电压。 第二电感元件连接在主开关元件和第一电容元件之间。 第二开关元件连接到第二电感元件和主开关元件的公共节点。 将第二开关元件连接到第一节点的第二电容元件提供第二升压输出电压。 辅助开关元件连接在第二电感元件和主开关元件的第一电感元件和公共节点之间。

公开(公告)号：US20120058628A1

公开(公告)日：2012-03-08

申请号：US13294526

申请日：2011-11-11

Applicant: Li-Shyue Lai ,  Jing-Cheng Lin

Inventor： Li-Shyue Lai ,  Jing-Cheng Lin

IPC: H01L21/20

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

Abstract translation: 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

公开(公告)号：US20120056315A1

公开(公告)日：2012-03-08

申请号：US12874952

申请日：2010-09-02

Applicant: Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

Inventor： Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Abstract translation: 一种器件包括衬底和包括穿透衬底的导电贯穿衬底通孔（TSV）的对准标记。