公开(公告)号：US09281243B2

公开(公告)日：2016-03-08

申请号：US14172832

申请日：2014-02-04

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/00 ,  H01L23/552 ,  B81B7/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/78 ,  B81B7/0064 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/11 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A chip scale package structure includes a chip, a dam unit, a board body, a plurality of first conductors, an encapsulating glue, a plurality of first conductive layers, an isolation layer, and a plurality of first electrodes. The dam unit is disposed on the surface of the chip. The board body is located on the dam unit. The first conductors are respectively in electrical contact with the conductive pads of the chip. The encapsulating glue covers the surface of the chip, and the board body and the first conductors are packaged in the encapsulating glue. The first conductive layers are located on the surface of the encapsulating glue opposite to the chip and respectively in electrical contact with the first conductors. The isolation layer is located on the encapsulating glue and the first conductive layers. The first electrodes are respectively in electrical contact with the first conductive layers.

Abstract translation: 芯片级封装结构包括芯片，堤坝单元，板体，多个第一导体，封装胶，多个第一导电层，隔离层和多个第一电极。 大坝单元设置在芯片的表面上。 板体位于坝体上。 第一导体分别与芯片的导电焊盘电接触。 封装胶覆盖芯片的表面，并且板体和第一导体封装在封装胶中。 第一导电层位于与芯片相对的封装胶的表面上，分别与第一导体电接触。 隔离层位于封装胶和第一导电层上。 第一电极分别与第一导电层电接触。

公开(公告)号：US09275958B2

公开(公告)日：2016-03-01

申请号：US14207224

申请日：2014-03-12

Applicant: XINTEC INC.

Inventor： Yi-Min Lin ,  Yi-Ming Chang ,  Shu-Ming Chang ,  Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L27/146 ,  H01L23/552 ,  H01L21/48 ,  H01L21/78 ,  H01L29/06 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 布置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中的导线层; 位于所述导线层和所述半导体基板之间的绝缘层; 以及设置在所述第一表面上并且具有至少一个孔的金属遮光层，其中所述至少一个孔的形状是四边形。

公开(公告)号：US09196594B2

公开(公告)日：2015-11-24

申请号：US14337121

申请日：2014-07-21

Applicant: XINTEC INC.

Inventor： Chao-Yen Lin ,  Yi-Hang Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/525 ,  H01L29/06 ,  G06K9/00 ,  H05K1/18

CPC classification number: H01L24/05 ,  G06K9/0004 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/525 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L29/06 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/0801 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/09445 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

公开(公告)号：US09165890B2

公开(公告)日：2015-10-20

申请号：US13941854

申请日：2013-07-15

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shih-Chin Chen ,  Yi-Ming Chang ,  Chien-Hui Chen ,  Chia-Ming Cheng ,  Wei-Luen Suen ,  Chen-Han Chiang

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/1416 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 设置在所述基板中的装置区域; 位于半导体衬底的第一表面上的电介质层; 位于所述电介质层中并电连接到所述器件区域的多个导电焊盘; 设置在所述半导体衬底中并且从所述第二表面朝向所述第一表面延伸的至少一个对准标记。

公开(公告)号：US09093450B2

公开(公告)日：2015-07-28

申请号：US14077877

申请日：2013-11-12

Applicant: XINTEC INC.

Inventor： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang

IPC: H01L21/50 ,  H01L25/00 ,  B81C1/00 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L25/50 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/0023 ,  B81C2203/0109 ,  B81C2203/0792 ,  H01L21/6835 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.

Abstract translation: 芯片封装包括具有上表面和下表面的衬底，并且包括：至少第一接触焊盘; 设置在上表面上的非光学传感器芯片，其中所述非光学传感器芯片至少包括第二接触焊盘并具有第一长度; 设置在所述非光学传感器芯片上的保护盖，其中所述保护盖具有第二长度，所述第二长度的延伸方向基本上平行于所述第一长度的延伸方向，并且所述第二长度短于所述第一长度; 设置在所述保护盖上的IC芯片，其中所述IC芯片包括至少第三接触焊盘并具有第三长度，并且所述第三长度的延伸方向基本上与所述第一长度的延伸方向平行; 以及在基板，非光学传感器芯片和IC芯片之间形成电连接的接合线。

公开(公告)号：US09013043B2

公开(公告)日：2015-04-21

申请号：US13667811

申请日：2012-11-02

Applicant: Xintec Inc.

Inventor： Hung-Chang Chen

IPC: H01L23/488 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/488 ,  H01L24/02 ,  H01L27/14618

Abstract: A semiconductor element includes: a transparent substrate; a stack structure formed on the transparent substrate and having a metal oxide layer partially exposed through sidewalls of the stack structure; a plurality of leads spacingly formed on the stack structure and extending to the sidewalls of the stack structure; an insulating film covering the exposed portions of the metal oxide layer; a metal film formed on the leads; and a solder mask layer disposed on the metal film, the stack structure and the insulating film. As such, the insulating film prevents short circuits from occurring between adjacent leads so as to improve the product yield.

Abstract translation: 半导体元件包括：透明基板; 形成在所述透明基板上并具有通过所述堆叠结构的侧壁部分露出的金属氧化物层的堆叠结构; 多个引线间隔地形成在堆叠结构上并延伸到堆叠结构的侧壁; 覆盖金属氧化物层的暴露部分的绝缘膜; 在引线上形成金属膜; 以及设置在金属膜，堆叠结构和绝缘膜上的焊料掩模层。 因此，绝缘膜防止相邻导线之间发生短路，从而提高产品产量。

公开(公告)号：US09006896B2

公开(公告)日：2015-04-14

申请号：US13887917

申请日：2013-05-06

Applicant: Xintec Inc.

Inventor： Yu-Lung Huang ,  Tsang-Yu Liu ,  Shu-Ming Chang

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/78 ,  B81B7/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/49811 ,  B81B7/007 ,  B81B2207/092 ,  B81B2207/095 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 导电焊盘结构，其位于所述电介质层中并电连接到所述器件区域，其中所述导电焊盘结构包括多个导电焊盘层的堆叠结构; 支撑层，设置在所述导电焊盘结构的顶表面上; 以及设置在半导体衬底的第二表面上的保护层。

公开(公告)号：US20140312478A1

公开(公告)日：2014-10-23

申请号：US14255883

申请日：2014-04-17

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2224/494 ,  H01L2224/8536 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和接合焊盘。 半导体芯片具有设置在下表面上的第一导电焊盘和对应于第一导电焊盘的第一孔。 第一孔和隔离层从上表面延伸到下表面以暴露第一导电垫。 再分布金属层设置在隔离层上并具有对应于第一导电焊盘的再分布金属线，再分布金属线通过开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘以将第一导电焊盘电连接到接合焊盘。 还提供了其方法。

公开(公告)号：US20140264771A1

公开(公告)日：2014-09-18

申请号：US14290638

申请日：2014-05-29

Applicant: XINTEC INC.

Inventor： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US20140251946A1

公开(公告)日：2014-09-11

申请号：US14282457

申请日：2014-05-20

Applicant: XINTEC INC.

Inventor： Yi-Ming CHANG ,  I-Min LIN ,  Po-Shen LIN

IPC: H05K3/06

CPC classification number: H05K3/06 ,  H01L21/4853 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.

Abstract translation: 提供了一种用于改善冠状缺陷的布线结构及其制造方法。 该方法包括以下步骤。 提供了其上形成有种子层和具有开口的图案化光致抗蚀剂层的衬底。 在开口中形成有覆盖种子层的底部的铜层。 覆盖铜层的至少一个顶部的阻挡层形成在铜层上。 阻挡层的氧化电位大于铜层的氧化电位。 去除图案化的光致抗蚀剂层以进行蚀刻工艺，其中铜层和暴露的种子层的一部分被蚀刻以形成布线层。 进行浸渍处理以在阻挡层和布线层的暴露表面上综合地形成抗氧化层。