公开(公告)号：US10157870B1

公开(公告)日：2018-12-18

申请号：US15716494

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Jing-Cheng Lin ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/12 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/31 ,  H01L21/683 ,  H01L23/532

Abstract: A method of fabricating an integrated fan-out package is described. The method includes the following steps. A carrier is provided. Through insulator vias are formed on the carrier, and at least one semiconductor die is provided on the carrier. The semiconductor die is attached to the carrier through a die attach film. An insulating encapsulant having a first region and a second region is formed on the carrier. The insulating encapsulant in the first region is encapsulating the semiconductor die, and the insulating encapsulant in the second region is encapsulating the plurality of through insulator vias. The carrier is debonded, and a trimming process is performed to remove portions of the insulating encapsulant in the second region, and a trench is formed in the insulating encapsulant in the second region. A plurality of conductive balls is disposed on the insulating encapsulant in the second region. The plurality of conductive balls surround the first region of the insulating encapsulant and the die attach film, and is electrically connected to the plurality of through insulator vias.

公开(公告)号：US10134719B2

公开(公告)日：2018-11-20

申请号：US15235118

申请日：2016-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/60

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.

公开(公告)号：US09960125B2

公开(公告)日：2018-05-01

申请号：US15219593

申请日：2016-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/03 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

Abstract: A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.

公开(公告)号：US20170373016A1

公开(公告)日：2017-12-28

申请号：US15235114

申请日：2016-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai

IPC: H01L23/552 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3142 ,  H01L23/481 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/105 ,  H01L2021/60022 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/14104 ,  H01L2224/1412 ,  H01L2224/73267 ,  H01L2225/06537 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/15311 ,  H01L2924/3025

Abstract: In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer conductive bump, a second package structure, a sealing material, and an electromagnetic interference (EMI) shielding layer. The first package structure has a first cut edge. The outer conductive bump is disposed on the first package structure and has a second cut edge. The second package structure is jointed onto the first package structure. The sealing material is disposed on the first package structure, surrounds the second package structure, and covers the outer conductive bump. The sealing material has a third cut edge. The EMI shielding layer contacts the first cut edge, the second cut edge and the third cut edge. The EMI shielding layer is electrically connected with the outer conductive bump.

公开(公告)号：US09698135B2

公开(公告)日：2017-07-04

申请号：US14990012

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L21/44 ,  H01L25/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4875 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/02 ,  H01L24/19 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02372 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for forming a package structure is provided. The method includes forming a plurality of conductive columns over a carrier substrate and forming an interfacial layer over sidewalls and tops of the conductive columns. The method also includes disposing a semiconductor die over a planar portion of the interfacial layer. The method further includes forming a molding compound to partially or completely encapsulate the semiconductor die, the conductive columns, and the interfacial layer such that the molding compound is in direct contact with the interfacial layer.

公开(公告)号：US09633924B1

公开(公告)日：2017-04-25

申请号：US14971132

申请日：2015-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Tsei-Chung Fu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L21/56 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/02

CPC classification number: H01L23/562 ,  H01L21/02068 ,  H01L21/02118 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/32051 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4864 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L33/62 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05005 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/0541 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.

公开(公告)号：US09299640B2

公开(公告)日：2016-03-29

申请号：US13943157

申请日：2013-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/06 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05563 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/08147 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80091 ,  H01L2224/80095 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first transistor formed in a front-side of the first semiconductor wafer, and the second semiconductor wafer includes a second transistor formed in a front-side of the second semiconductor wafer. A backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device structure further includes an interconnect structure formed over the front-side of the second semiconductor wafer, and at least one first through substrate via (TSV) directly contacts a conductive feature of the first semiconductor wafer and the interconnect structure.

Abstract translation: 提供了形成半导体器件结构的机构的实施例。 半导体器件结构包括第一半导体晶片和第二半导体晶片。 第一半导体晶片包括形成在第一半导体晶片的前侧的第一晶体管，第二半导体晶片包括形成在第二半导体晶片的前侧的第二晶体管。 第二半导体晶片的背面接合到第一半导体晶片的正面。 半导体器件结构还包括形成在第二半导体晶片的前侧上的互连结构，并且至少一个第一贯穿衬底通孔（TSV）直接接触第一半导体晶片的导电特征和互连结构。

公开(公告)号：US20150021741A1

公开(公告)日：2015-01-22

申请号：US13945217

申请日：2013-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L29/06 ,  H01L21/02

CPC classification number: H01L21/02104 ,  H01L21/2007 ,  H01L21/76254 ,  H01L21/8221 ,  H01L23/481 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method is disclosed that includes the steps outlined below. An epitaxial layer is formed on a first semiconductor substrate. At least one implant species is implanted between the epitaxial layer and the first semiconductor substrate to form an ion-implanted layer. The epitaxial layer is bonded to a bonding oxide layer of a second semiconductor substrate. The first semiconductor substrate is separated from the ion-implanted layer.

Abstract translation: 公开了一种包括以下概述的步骤的方法。 在第一半导体衬底上形成外延层。 在外延层和第一半导体衬底之间注入至少一种植入物种以形成离子注入层。 外延层与第二半导体衬底的结合氧化物层结合。 第一半导体衬底与离子注入层分离。

公开(公告)号：US20140084476A1

公开(公告)日：2014-03-27

申请号：US13624620

申请日：2012-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin ,  Shih-Yi Syu

IPC: H01L23/48

CPC classification number: H01L23/367 ,  H01L21/4882 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/0756 ,  H01L2224/13 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/181 ,  H01L2924/00

Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.

Abstract translation: 芯片包括半导体衬底，穿透半导体衬底的贯穿通孔，覆盖并连接到通孔的密封环，以及位于半导体衬底下方的电连接器，并通过通孔电耦合到密封环。