公开(公告)号：US20100116536A1

公开(公告)日：2010-05-13

申请号：US12379056

申请日：2009-02-11

Applicant: Myung Sam Kang

Inventor： Myung Sam Kang

IPC: H05K1/11 ,  B32B38/10 ,  B32B38/00

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2201/09736 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00

Abstract: Disclosed is a printed circuit board having a buried solder bump, in which a circuit pattern and a solder bump formed on the circuit pattern are buried in an insulating layer, thus improving the degree of matching between the solder bump and the circuit pattern and obviating a need for an additional coining process of the solder bump. A manufacturing method thereof is also provided.

Abstract translation: 公开了一种具有掩埋焊料凸块的印刷电路板，其中形成在电路图案上的电路图案和焊料凸块被掩埋在绝缘层中，从而提高了焊料凸块与电路图案之间的匹配程度，并且消除了 需要额外的冲压焊过程。 还提供了其制造方法。

公开(公告)号：US20090321387A1

公开(公告)日：2009-12-31

申请号：US12273961

申请日：2008-11-19

Applicant: Myung-Sam KANG

Inventor： Myung-Sam KANG

IPC: B44C1/22

CPC classification number: H05K3/421 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/427 ,  H05K3/4652 ,  H05K2201/0341 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/1388

Abstract: Disclosed is a manufacturing method of a printed circuit board. The method in accordance with an embodiment of the present invention includes: providing a laminated substrate having an insulator as well as a first metal layer and a second metal layer, which are sequentially laminated on one side of the insulator; processing a via hole in the laminated substrate; forming a seed layer on an inner wall of the via hole and on a surface of the second metal layer; plating an inside of the via hole and the surface of the second metal layer with a conductive material that is different from a material of the second metal layer; etching the seed layer and the conductive material, formed on the second metal layer; etching the second metal layer; and forming a first circuit pattern by selectively etching the first metal layer.

Abstract translation: 公开了一种印刷电路板的制造方法。 根据本发明的实施例的方法包括：提供具有绝缘体的层叠基板以及依次层压在绝缘体的一侧上的第一金属层和第二金属层; 处理层压基板中的通孔; 在所述通孔的内壁上和所述第二金属层的表面上形成种子层; 用与第二金属层的材料不同的导电材料电镀通孔内表面和第二金属层表面; 蚀刻形成在第二金属层上的种子层和导电材料; 蚀刻第二金属层; 以及通过选择性地蚀刻所述第一金属层来形成第一电路图案。

公开(公告)号：US07562446B2

公开(公告)日：2009-07-21

申请号：US11524403

申请日：2006-09-21

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/4652 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/4697 ,  H05K2201/09536 ,  H05K2203/0191 ,  H05K2203/063 ,  H05K2203/308 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit patter on both sides of a seed layer by use of a first dry film, the seed layer being for forming a circuit pattern on both sides; (b) laminating a second dry film on the first dry film on both sides of the seed layer, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed on both sides of the seed layer, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method for manufacturing a substrate with a cavity in accordance with the present invention can improve the efficiency of a substrate manufacturing process by using both sides of a seed layer to manufacture the substrate with a cavity.

Abstract translation: 公开了一种用于制造具有空腔的衬底的方法。 该方法包括：（a）通过使用第一干膜在种子层的两侧形成第一电路图案，种子层用于在两侧形成电路图案; （b）在种子层两侧的第一干膜上层叠第二干膜，第二干膜的厚度对应于待形成的空腔的深度; （c）在种子层的两侧上在要形成空腔的区域之外的区域层叠电介质层，电介质层的厚度对应于待形成的空腔的深度; （d）在种子层上层叠具有第二电路图案的铜箔层叠主板; 和（e）通过在去除种子层之后剥离第一干膜和第二干膜来形成空腔。 根据本发明的用于制造具有空腔的基板的方法可以通过使用种子层的两面来制造具有空腔的基板来提高基板制造工艺的效率。

公开(公告)号：US07516545B2

公开(公告)日：2009-04-14

申请号：US11591586

申请日：2006-11-02

Applicant: Myung Sam Kang ,  Shuhichi Okabe ,  Jung Hyun Park ,  Hoe Ku Jung ,  Ji Eun Kim

Inventor： Myung Sam Kang ,  Shuhichi Okabe ,  Jung Hyun Park ,  Hoe Ku Jung ,  Ji Eun Kim

IPC: H01K3/10 ,  H05K3/02

CPC classification number: H05K1/116 ,  H05K3/0094 ,  H05K3/421 ,  H05K3/428 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a method of manufacturing a printed circuit board having a landless via hole. Specifically, this invention provides a method of manufacturing a printed circuit board having a landless via hole without the upper land of a via hole using a photoresist (P-LPR) which is loaded in the via hole. Therefore, in this invention, since a circuit pattern is formed using only copper of a copper clad laminate, the width thereof is minimized, thus easily realizing a fine circuit pattern. Further, the landless via hole structure is applied, resulting in a highly dense circuit pattern.

Abstract translation: 公开了一种具有无地过孔的印刷电路板的制造方法。 具体而言，本发明提供一种制造印刷电路板的方法，所述印刷电路板具有无通孔通孔，所述无通孔通孔使用装载在所述通孔中的光致抗蚀剂（P-LPR）而不具有通孔的上部焊盘。 因此，在本发明中，由于仅使用覆铜层压板的铜形成电路图案，所以其宽度被最小化，因此容易实现精细电路图案。 此外，施加无地通孔结构，导致高度密集的电路图案。

公开(公告)号：US20090056119A1

公开(公告)日：2009-03-05

申请号：US12005610

申请日：2007-12-28

Applicant: Shuhichi Okabe ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Myung Sam Kang ,  Jung Hyun Park ,  Ji Hong Jo ,  Jin Yong An ,  Soon Oh Jung

Inventor： Shuhichi Okabe ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Myung Sam Kang ,  Jung Hyun Park ,  Ji Hong Jo ,  Jin Yong An ,  Soon Oh Jung

IPC: H05K3/00

CPC classification number: H05K3/205 ,  H05K3/062 ,  H05K3/108 ,  H05K3/462 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/061 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a method of fabricating a multilayer printed circuit board, which enables the formation of a micro circuit able to be realized through a semi-additive process using the CTE and rigidity of a metal carrier on a thin substrate which is difficult to convey.

Abstract translation: 公开了一种制造多层印刷电路板的方法，其能够形成能够通过使用CTE的半添加工艺和难以传送的薄基板上的金属载体的刚性来实现的微电路。

公开(公告)号：US07485569B2

公开(公告)日：2009-02-03

申请号：US11137345

申请日：2005-05-24

Applicant: Chang Sup Ryu ,  Doo Hwan Lee ,  Jin Yong Ahn ,  Myung Sam Kang ,  Suk Hyeon Cho

Inventor： Chang Sup Ryu ,  Doo Hwan Lee ,  Jin Yong Ahn ,  Myung Sam Kang ,  Suk Hyeon Cho

IPC: H01L21/4763

CPC classification number: H01L23/5389 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/82039 ,  H01L2924/01078 ,  H01L2924/01087 ,  H05K1/186 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2203/0191

Abstract: A printed circuit board having embedded chips, composed of a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a via hole filled with conductive ink, and a circuit layer formed on the insulating layer and having a via hole and a circuit pattern electrically connected to the chip of the central layer through the via hole of the insulating layer. In addition, a method of fabricating a printed circuit board including embedded chips is provided.

Abstract translation: 一种具有嵌入式芯片的印刷电路板，由具有嵌入式芯片的中心层，形成在中心层的一个表面或两个表面上的绝缘层，并且具有填充有导电油墨的通孔，以及形成在绝缘体上的电路层 并且具有通孔和通过绝缘层的通孔与中心层的芯片电连接的电路图案。 此外，提供了一种制造包括嵌入式芯片的印刷电路板的方法。

公开(公告)号：US20090008143A1

公开(公告)日：2009-01-08

申请号：US12155838

申请日：2008-06-10

Applicant: Jin-Yong Ahn ,  Chang-Sup Ryu ,  Byung-Youl Min ,  Myung-Sam Kang

Inventor： Jin-Yong Ahn ,  Chang-Sup Ryu ,  Byung-Youl Min ,  Myung-Sam Kang

IPC: H01K3/22 ,  H01R12/04

CPC classification number: H05K3/107 ,  H05K3/205 ,  H05K3/465 ,  H05K3/4658 ,  H05K2201/0191 ,  H05K2201/0376 ,  Y10T29/49158

Abstract: A board having buried patterns is disclosed. The board may include an insulation panel, a first pattern buried in one side of the insulation panel, a second pattern buried in the other side of the insulation panel with a predetermined insulating thickness between the first pattern and the second pattern, and a via which electrically connects the first pattern and the second pattern. The board having buried patterns according to certain embodiments of the invention can have greater rigidity compared to a board having exposed patterns, for the same insulating thickness. Also, a carrier-insulation set having a particular amount of thickness can be utilized to satisfy the thickness requirement in employing an existing roller apparatus intended for thicker boards.

Abstract translation: 公开了具有掩埋图案的板。 板可以包括绝缘板，埋在绝缘板的一侧中的第一图案，在第一图案和第二图案之间以预定的绝缘厚度掩埋在绝缘板的另一侧中的第二图案，以及通孔， 电连接第一图案和第二图案。 对于相同的绝缘厚度，具有根据本发明的某些实施例的埋设图案的板可以具有比具有暴露图案的板更大的刚性。 此外，可以利用具有特定厚度的载体绝缘组件来满足使用用于较厚板的现有辊装置的厚度要求。

公开(公告)号：US20080264684A1

公开(公告)日：2008-10-30

申请号：US12003669

申请日：2007-12-28

Applicant: Myung Sam Kang ,  Byoung Youl Min ,  Je Gwang Yoo ,  Jung Hyun Park ,  Chang Sup Ryu ,  Jin Yong Ahn

Inventor： Myung Sam Kang ,  Byoung Youl Min ,  Je Gwang Yoo ,  Jung Hyun Park ,  Chang Sup Ryu ,  Jin Yong Ahn

IPC: H05K3/10 ,  H05K1/00 ,  H05K1/11

CPC classification number: H05K3/428 ,  H05K3/205 ,  H05K3/383 ,  H05K3/384 ,  H05K3/4602 ,  H05K3/4658 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/1536 ,  Y10T29/49155

Abstract: Disclosed herein is a carrier member for transmitting circuits, which is a component of a coreless printed circuit board having circuit patterns embedded therein, and which can be used to provide a high-density and highly reliable printed circuit board by forming protrusions only on the lower ends of the circuit patterns, a coreless printed circuit board using the carrier member, and methods of manufacturing the carrier member and the coreless printed circuit board.

Abstract translation: 本文公开了一种用于传输电路的载体构件，其是具有嵌入其中的电路图案的无芯印刷电路板的部件，其可用于通过仅在下部形成突起来提供高密度和高可靠性的印刷电路板 电路图案的端部，使用载体部件的无芯印刷电路板，以及制造载体部件和无芯印刷电路板的方法。

公开(公告)号：US07394249B2

公开(公告)日：2008-07-01

申请号：US10965613

申请日：2004-10-14

Applicant: Myung-Sam Kang ,  Chang-Sup Ryu ,  Won-Cheol Bae ,  Jae-Kul Lee ,  Doo-Hwan Lee

Inventor： Myung-Sam Kang ,  Chang-Sup Ryu ,  Won-Cheol Bae ,  Jae-Kul Lee ,  Doo-Hwan Lee

IPC: G01R33/04

CPC classification number: G01R33/04 ,  H05K1/165 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/086 ,  H05K2201/10151

Abstract: Disclosed is a printed circuit board with a weak magnetic field sensor according to the present invention, which includes a substrate having first excitation circuits and first detection circuits formed on both sides thereof. First laminates are layered on both sides of the substrate, and have soft magnetic cores with a predetermined shape formed thereon. Second laminates are layered on the first laminates, and have second excitation circuits and second detection circuits, connected through via holes to the first excitation circuits and first detection circuits, respectively, so that the first and second excitation circuits and first and second detection circuits are wound around the soft magnetic cores, formed thereon. The soft magnetic cores each include a magnetic core and non-magnetic metal layers formed on both sides of the magnetic core.

Abstract translation: 公开了根据本发明的具有弱磁场传感器的印刷电路板，其包括具有形成在其两侧上的第一激励电路和第一检测电路的基板。 第一层压体层叠在基板的两侧，并且具有形成在其上的预定形状的软磁芯。 第二层叠体层叠在第一层叠体上，并具有分别通过通孔与第一激励电路和第一检测电路连接的第二激励电路和第二检测电路，使得第一和第二激励电路以及第一和第二检测电路 缠绕在其上形成的软磁芯上。 软磁芯各自包括形成在磁芯两侧的磁芯和非磁性金属层。

公开(公告)号：US20080098597A1

公开(公告)日：2008-05-01

申请号：US11976072

申请日：2007-10-19

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K3/02

CPC classification number: H05K3/20 ,  H05K3/0058 ,  H05K3/108 ,  H05K3/4611 ,  H05K3/4682 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of manufacturing a circuit board is disclosed. A method of manufacturing a circuit board that includes forming a first circuit pattern on the insulation layer of a carrier, in which an insulation layer and a first seed layer are stacked in order; stacking and pressing the carrier and an insulation board with the side of the carrier having the first circuit pattern facing the insulation board; removing the carrier to transfer the first circuit pattern and the insulation layer onto the insulation board; and forming a second circuit pattern on the insulation layer transferred to the insulation board, allows fine pitch circuit patterns to enable the manufacture of fine circuit patterns of high density on the board, and allows the manufacture of a multi-layer circuit board with a simple process.

Abstract translation: 公开了一种制造电路板的方法。 一种制造电路板的方法，包括在载体的绝缘层上形成第一电路图案，其中绝缘层和第一种子层依次层叠; 堆叠并按压载体和绝缘板，其中载体侧具有面向绝缘板的第一电路图案; 移除载体以将第一电路图案和绝缘层转移到绝缘板上; 并且在转移到绝缘板的绝缘层上形成第二电路图案，允许精细的间距电路图案能够在板上制造高密度的精细电路图案，并且允许制造具有简单的多层电路板 处理。