公开(公告)号：US07033882B2

公开(公告)日：2006-04-25

申请号：US10760080

申请日：2004-01-15

Applicant: Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

Inventor： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/8242

CPC classification number: H01L28/75 ,  H01L21/28568 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/53238 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling. In order to facilitate the removal of photoresist by an oxygen plasma process prior to exposing copper conductors during the capacitor stack etch, an Al hardmask can be used to protect the capacitor formed with Ta2O5 dielectric, or a W hardmask can be used to protect the capacitor formed with BST dielectric.

Abstract translation: 公开了片上去耦电容器结构以及制造这种去耦电容器的方法。 片内去耦电容有助于在高浪涌电流条件下降低或防止电网上的L di / dt电压下降。 将一个或多个去耦电容器包含在靠近电力电网导体的芯片上减小了寄生电感，从而提供了相对于高频噪声的改进的去耦性能。 在本发明的一个实施例中，在金属互连层之间插入电容器堆叠结构。 这样的电容器堆叠可以由底部电极/屏障组成; 具有高介电常数的薄介电材料; 和顶部电极/屏障。 在替代实施例中，底部电极和/或底部金属互连层具有三维结构以增加电容器的表面积。 体现本发明的说明性方法包括制造片上去耦电容器堆叠结构并电连接电容器以提供有效的电容去耦合。 为了在电容器堆叠蚀刻期间在铜导体暴露之前通过氧​​等离子体工艺促进光致抗蚀剂的去除，可以使用Al硬掩模来保护由Ta 2 O 5形成的电容器 电介质或W硬掩模可用于保护由BST电介质形成的电容器。

公开(公告)号：US20060003548A1

公开(公告)日：2006-01-05

申请号：US10898400

申请日：2004-07-23

Applicant: Mauro Kobrinsky ,  Shriram Ramanathan ,  Scott List

Inventor： Mauro Kobrinsky ,  Shriram Ramanathan ,  Scott List

IPC: H01L21/30

CPC classification number: H01L21/67092 ,  H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/17 ,  H01L2224/75 ,  H01L2224/7511 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/81011 ,  H01L2224/81012 ,  H01L2224/81013 ,  H01L2224/81121 ,  H01L2224/81209 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/3511

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

公开(公告)号：US06908565B2

公开(公告)日：2005-06-21

申请号：US10328958

申请日：2002-12-24

Applicant: Sarah E. Kim ,  R. Scott List

Inventor： Sarah E. Kim ,  R. Scott List

IPC: H01L21/20 ,  H01L21/306 ,  H01L25/065 ,  H01L21/00

CPC classification number: H01L25/0657 ,  H01L21/2007 ,  H01L21/30604 ,  H01L21/30608 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include etching away unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.

Abstract translation: 在堆叠的微电子器件的制造中，用于薄化晶片到晶片垂直叠层的方法。 所述方法包括蚀刻在垂直叠层中待薄化的晶片的未支撑部分。 未支撑部分的去除基本上消除了晶片的潜在的破裂和碎裂，当存在未支撑的部分时，这可能在稀化过程中发生。

公开(公告)号：US06888716B2

公开(公告)日：2005-05-03

申请号：US10767559

申请日：2004-01-28

Applicant: Richard Scott List ,  Bruce A. Block ,  Mark T. Bohr

Inventor： Richard Scott List ,  Bruce A. Block ,  Mark T. Bohr

IPC: H01L21/02 ,  H01L21/60 ,  H01L23/522 ,  H01L27/08 ,  H01G4/228

CPC classification number: H01L24/11 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/75 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01038 ,  H01L2924/01044 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

Abstract translation: 公开了一种制造片上去耦电容器的方法，其有助于防止在高浪涌电流条件下电网上的L di / dt电压下降。 在电网之间直接插入去耦电容器大大降低了电感L，并提供去耦以减少最高可能的频率噪声。 本发明具体描述了其中去耦电容器位于顶层金属化和具有多个开口或棒几何形状以提供电网和顶部去耦电容器电极接触的标准突起触头之间的工艺流程。

公开(公告)号：US06887769B2

公开(公告)日：2005-05-03

申请号：US10066645

申请日：2002-02-06

Applicant: Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

Inventor： Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

IPC: H01L21/30 ,  H01L21/302 ,  H01L21/46 ,  H01L21/461 ,  H01L21/60 ,  H01L21/98 ,  H01L23/48 ,  H01L23/485 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L23/481 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/2919 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.

Abstract translation: 三维（3-D）集成芯片系统具有包括一个或多个集成电路（IC）装置的第一晶片; 包括一个或多个集成电路（IC）装置的第二晶片; 以及在指定位置处沉积在第一和第二晶片的相对表面上的金属线，其中包围金属线的层间电介质（ILD）凹槽以促进第一和第二晶片之间的直接金属接合，并建立第一和第二晶片上的有源IC器件之间的电连接 和第二晶片。

公开(公告)号：US20050079685A1

公开(公告)日：2005-04-14

申请号：US10683202

申请日：2003-10-09

Applicant: Shriram Ramanathan ,  Grant Kloster ,  Patrick Morrow ,  Vijayakumar RamachandraRao ,  Scott List

Inventor： Shriram Ramanathan ,  Grant Kloster ,  Patrick Morrow ,  Vijayakumar RamachandraRao ,  Scott List

IPC: H01L21/46 ,  H01L23/485 ,  H01L25/065

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14

Abstract: The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.

Abstract translation: 本发明提供了具有降低的故障的堆叠晶片结构。 在一个实施例中，存在沉积在导体的暴露表面上的阻挡层，其延伸跨越第一和第二器件结构之间的距离。 阻挡层可以防止导体材料的扩散和电迁移，这可能降低层叠晶片结构中的短路和空隙的发生。

公开(公告)号：US06790748B2

公开(公告)日：2004-09-14

申请号：US10326206

申请日：2002-12-19

Applicant: Sarah E. Kim ,  R. Scott List ,  Mauro J. Kobrinsky

Inventor： Sarah E. Kim ,  R. Scott List ,  Mauro J. Kobrinsky

IPC: H01L2176

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L23/481 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/15311 ,  Y10S438/977 ,  H01L2924/014 ,  H01L2224/05599

Abstract: Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include physically removing unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.

Abstract translation: 在堆叠的微电子器件的制造中，用于薄化晶片到晶片垂直叠层的方法。 这些方法包括在垂直堆叠中物理去除待稀释的晶片的未支撑部分。 未支撑部分的去除基本上消除了晶片的潜在的破裂和碎裂，当存在未支撑的部分时，这可能在稀化过程中发生。

公开(公告)号：US06706584B2

公开(公告)日：2004-03-16

申请号：US09895362

申请日：2001-06-29

Applicant: Richard Scott List ,  Bruce A. Block ,  Mark T. Bohr

Inventor： Richard Scott List ,  Bruce A. Block ,  Mark T. Bohr

IPC: H01L218242

CPC classification number: H01L24/11 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/75 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01038 ,  H01L2924/01044 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

Abstract translation: 公开了一种制造片上去耦电容器的方法，其有助于防止在高浪涌电流条件下电网上的L di / dt电压下降。 在电网之间直接插入去耦电容器大大降低了电感L，并提供去耦以减少最高可能的频率噪声。 本发明具体描述了其中去耦电容器位于顶层金属化和具有多个开口或棒几何形状以提供电网和顶部去耦电容器电极接触的标准突起触头之间的工艺流程。

公开(公告)号：US6127203A

公开(公告)日：2000-10-03

申请号：US304953

申请日：1999-05-05

Applicant: Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

Inventor： Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

IPC: H01L21/58 ,  H01L21/324

CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/351

Abstract: This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.

Abstract translation: 本发明涉及将集成电路（IC）安装到多芯片模块（MCM）或基板上。 更具体地，它提供了一种将半导体管芯如汞碲化镉（MCT）的薄片安装到硅半导体衬底，读出集成电路（ROIC），使用热塑性材料以减少MCT上的应力的方法， 通过不匹配的热膨胀系数（CTE）。 该过程提供了在诸如MCT的材料上的红外光电检测器阵列，其将使用针对FPAs的垂直集成光电二极管（VIP）方法安装到读出集成电路（ROIC），同时允许CdTe用于表面钝化的双面相互扩散 以减少暗电流并提高性能，而没有与高温过程中热膨胀系数不匹配相关的问题。

公开(公告)号：US07696015B2

公开(公告)日：2010-04-13

申请号：US11448232

申请日：2006-06-07

Applicant: Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

Inventor： Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

IPC: H01L21/20 ,  H01L21/48 ,  H01L21/44

CPC classification number: F04B17/00 ,  F04B19/006 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06589 ,  H01L2924/01322

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract translation: 一组发热集成电路芯片可以设置有中间冷却集成电路芯片。 冷却集成电路芯片可以包括用于冷却流体流动的微通道。 可以使用集成的电渗泵泵送冷却流体。 在一些实施方案中，使用集成的重组合器可以实现冷却流体气体的去除。