公开(公告)号：US20160124308A1

公开(公告)日：2016-05-05

申请号：US14533464

申请日：2014-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guoxiang NING ,  Xintuo DAI ,  Huang LIU ,  Chin Teong LIM

IPC: G03F7/20 ,  G03F7/00

CPC classification number: G03F7/0035 ,  G03F7/094 ,  G03F7/2024 ,  G03F7/203

Abstract: Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material.

Abstract translation: 促进电路结构的制造，其中使用第一掩模进行多层结构的第一曝光，第一掩模限定要形成在多层结构的基板上方的元件的至少一个边缘的定位。 使用限定元件的至少一个其它边缘的定位的第二掩模来执行多层结构的第二曝光。 至少部分地使用所述元件的至少一个边缘和所述至少一个其它边缘的限定的定位来移除所述多层结构的至少一些材料，以在所述基底上方形成所述元件。 在一些示例中，形成多个元件，多个元件是硬掩模元件，以便蚀刻工艺来蚀刻衬底材料。

公开(公告)号：US20150332934A1

公开(公告)日：2015-11-19

申请号：US14281359

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  Xiang HU ,  Zhao LUN ,  Huang LIU

IPC: H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L29/12 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/0684 ,  H01L29/12 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.

Abstract translation: 诸如FinFET的非平面半导体结构的凸起结构（例如，翅片）上的光刻叠层包括旋涂非晶碳或旋涂有机平面化材料的底层，氮化物的硬掩模层 和/或旋涂层上的氧化物，硬掩模层上的可显影底部抗反射涂层（dBARC）的层和光致抗蚀剂的顶层。 蚀刻该叠层以露出和凹进凸起的结构，并且外延结构在凹槽上生长。

公开(公告)号：US20150295047A1

公开(公告)日：2015-10-15

申请号：US14252447

申请日：2014-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou HUANG ,  Huang LIU ,  Jin Ping LIU

IPC: H01L29/165 ,  H01L21/02 ,  H01L29/267 ,  H01L29/06 ,  H01L29/205 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111

Abstract: A defect-free, relaxed semiconductor covering layer (e.g., epitaxial SiGe) over a semiconductor substrate (e.g., Si) is provided having a strain relaxation degree above about 80% and a non-zero threading dislocation density of less than about 100/cm2. A lattice mismatch exists between the substrate and the covering layer. The covering layer also has a non-zero thickness that may be less than about 0.5 microns. The strain relaxation degree and threading dislocation are achieved by exposing defects at or near a surface of an initial semiconductor layer on the substrate (i.e., exposing defects via selective etch and filling-in any voids created), planarizing the filled-in surface, and creating the covering layer (e.g., growing epitaxy) on the planarized, filled-in surface, which is also planarized.

Abstract translation: 提供半导体衬底（例如Si）上的无缺陷的，松弛的半导体覆盖层（例如，外延SiGe），其具有高于约80％的应变松弛度和小于约100 / cm 2的非零穿透位错密度 。 衬底和覆盖层之间存在晶格失配。 覆盖层还具有可以小于约0.5微米的非零厚度。 应变松弛度和穿透位错是通过在基板上的初始半导体层的表面处或附近暴露缺陷来实现的（即，通过选择性蚀刻暴露缺陷并填充所产生的任何空隙），平坦化填充表面，以及 在平坦化的填充表面上形成覆盖层（例如，生长外延），其也被平坦化。

公开(公告)号：US20150140751A1

公开(公告)日：2015-05-21

申请号：US14085906

申请日：2013-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Huang LIU ,  Lun ZHAO ,  Richard J. CARTER

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Abstract translation: 提供了电路制造方法，其包括例如：为电路结构提供在衬底结构的第一区域和第二区域上延伸的至少一个栅极结构，所述至少一个栅极结构包括封盖层; 以及修改所述至少一个栅极结构的覆盖层的至少一部分的蚀刻特性，其中所述修改的蚀刻性能在第一蚀刻工艺期间禁止蚀刻所述至少一个栅极结构，促进制造至少一个第一晶体管 所述第一区域并且在第二蚀刻工艺期间抑制所述至少一个栅极结构的蚀刻，促进在所述第二区域中制造至少一个第二晶体管。

公开(公告)号：US20150104948A1

公开(公告)日：2015-04-16

申请号：US14050472

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. PATIL ,  Huy CAO ,  Hui ZHAN ,  Huang LIU

IPC: H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/31105 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66795

Abstract: Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.

Abstract translation: 提供了便于制造电路结构的方法，其包括例如：提供具有膜层的结构; 通过将至少一种元素或分子注入到膜层的上部来改变膜层的蚀刻性质，膜层的蚀刻性质在上部保持不变; 并且对具有改进的蚀刻特性的结构和膜层进行蚀刻处理，使得蚀刻处理的膜层的改性蚀刻性能得以改善。 修改膜层上部的蚀刻性能可以包括使薄膜层的上部优先易于或优先地抵抗蚀刻工艺，这取决于促进的电路制造方法。

公开(公告)号：US20140327139A1

公开(公告)日：2014-11-06

申请号：US13875377

申请日：2013-05-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jialin YU ,  Jilin XIA ,  Huang LIU ,  Wonwoo KIM ,  Changyong XIAO

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Contact structures and methods of fabricating contact structures of semiconductor devices are provided. One method includes, for instance: obtaining a substrate including a dielectric layer over the substrate; patterning the dielectric layer with at least one contact opening; providing a contact liner within the at least one contact opening in the dielectric layer; and filling the contact liner with a conductive material. In enhanced aspects, providing the contact liner within the at least one contact opening includes: depositing a first layer within the at least one contact opening in the dielectric layer; depositing a second layer over the first layer within the at least one contact opening; depositing at least one intermediate layer over the second layer within the at least one contact opening; and depositing a top layer over the at least one intermediate layer within the at least one contact opening.

Abstract translation: 提供了制造半导体器件的接触结构的接触结构和方法。 一种方法包括例如：在衬底上获得包括电介质层的衬底; 用至少一个接触开口构图介电层; 在所述电介质层中的所述至少一个接触开口内提供接触衬垫; 并用导电材料填充接触衬垫。 在增强的方面，在所述至少一个接触开口内提供所述接触衬垫包括：在所述电介质层中的所述至少一个接触开口内沉积第一层; 在所述至少一个接触开口内的第一层上沉积第二层; 在所述至少一个接触开口内沉积所述第二层上的至少一个中间层; 以及在所述至少一个接触开口内的所述至少一个中间层上沉积顶层。

公开(公告)号：US20190139830A1

公开(公告)日：2019-05-09

申请号：US15802795

申请日：2017-11-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Minoli K. PATHIRANE ,  Chanro PARK ,  Guillaume BOUCHE ,  Nigel CAVE ,  Mahender KUMAR ,  Min Gyu SUNG ,  Huang LIU ,  Hui ZANG

IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78

Abstract: Fin field effect transistors (FinFETs) and their methods of manufacture include a self-aligned gate isolation layer. A method of forming the FinFETs includes the formation of sacrificial spacers over fin sidewalls, and the formation of an isolation layer between adjacent fins at self-aligned locations between the sacrificial spacers. An additional layer such as a sacrificial gate layer is formed over the isolation layer, and photolithography and etching techniques are used to cut, or segment, the additional layer to define a gate cut opening over the isolation layer. The gate cut opening is backfilled with a dielectric material, and the backfilled dielectric and the isolation layer cooperate to separate neighboring sacrificial gates and hence the later-formed functional gates associated with respective devices.

公开(公告)号：US20170200792A1

公开(公告)日：2017-07-13

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho MAENG ,  Andy WEI ,  Anthony OZZELLO ,  Bharat KRISHNAN ,  Guillaume BOUCHE ,  Haifeng SHENG ,  Haigou HUANG ,  Huang LIU ,  Huy M. CAO ,  Ja-Hyung HAN ,  SangWoo LIM ,  Kenneth A. BATES ,  Shyam PAL ,  Xintuo DAI ,  Jinping LIU

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US20170047282A1

公开(公告)日：2017-02-16

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo SUN ,  Qiang FANG ,  Huang LIU ,  Haigou HUANG ,  Jiehui SHU ,  Jin Ping LIU

IPC: H01L23/528 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。

公开(公告)号：US20160125121A1

公开(公告)日：2016-05-05

申请号：US14533497

申请日：2014-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Xintuo DAI ,  Huang LIU ,  Chin Teong LIM

IPC: G06F17/50 ,  G03F7/34 ,  G03F7/32 ,  G03F7/16 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F1/54 ,  G03F1/70 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/34

Abstract: Achieving a critical dimension target for a feature based on characteristics of a resist is facilitated. Mask data is established for fabricating a lithographic mask to expose different regions of a resist to high, low, and intermediate exposure levels. The resist is configured to exhibit high solubility when exposed to the high or low exposure level, and low solubility when exposed to the intermediate exposure level. A critical dimension for a region of the resist to be exposed to the intermediate exposure level is determined, and the mask data is established to indicate opaque regions for forming on the lithographic mask. The opaque regions are arrayed to facilitate exposing the region of the resist to the intermediate exposure level, to achieve the determined critical dimension. Further, a method is provided for forming in-situ a patterned mask from a mask layer above a substrate material.

Abstract translation: 实现基于抗蚀剂特性的特征的关键尺寸目标。 建立掩模数据用于制造光刻掩模以将抗蚀剂的不同区域暴露于高，低和中等曝光水平。 抗蚀剂被配置为当暴露于高或低曝光水平时表现出高溶解度，并且当暴露于中等曝光水平时具有低溶解度。 确定抗蚀剂暴露于中间曝光水平的区域的关键尺寸，并且建立掩模数据以指示用于在光刻掩模上形成的不透明区域。 排列不透明区域以便于将抗蚀剂的区域暴露于中间曝光水平，以获得确定的临界尺寸。 此外，提供了一种用于从衬底材料上方的掩模层原位形成图案化掩模的方法。