公开(公告)号：US09585257B2

公开(公告)日：2017-02-28

申请号：US14668031

申请日：2015-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sudeep Mandal ,  David J. Russell

IPC: H05K3/02 ,  H05K3/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/373 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H01L21/60

CPC classification number: H05K3/0094 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76877 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2021/60007 ,  H01L2224/16225 ,  H05K1/0201 ,  H05K1/115 ,  H05K3/4038

Abstract: The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having thermally conductive vias in addition to electrically conductive vias. The thermally conductive vias help dissipate heat from one or more IC chips, through the glass interposer, into an organic carrying, and then, into an underlying substrate where it can be dissipated.

Abstract translation: 本发明一般涉及集成电路（IC）芯片封装，更具体地，涉及一种形成具有导电通孔的玻璃插入件以及导电通孔的结构和方法。 导热通孔有助于从一个或多个IC芯片（通过玻璃插入件）将热量散发到有机载体中，然后进入可以被耗散的底层基板。

公开(公告)号：US20210033660A1

公开(公告)日：2021-02-04

申请号：US16527146

申请日：2019-07-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sebastian T. Ventrone ,  Richard S. Graf ,  Ezra D. B. Hall ,  Jack R. Smith

IPC: G01R31/28 ,  H04L9/32

Abstract: An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.

公开(公告)号：US09368425B2

公开(公告)日：2016-06-14

申请号：US14135991

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Richard S. Graf ,  Jay F. Leonard ,  David J. West ,  Charles H. Wilson

IPC: H01L29/00 ,  H01L23/433 ,  H01L23/64 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4334 ,  H01L23/49816 ,  H01L23/645 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the invention relate to incorporating one or more antennas or inductor coils into a semi-conductor package. A heat spreader or metal sheet is embedded in the package and stamped or otherwise patterned into a spiral or serpentine form. The pattern enables the spreader to function as an inductor or antenna when connected to a semiconductor chip in communication with a printed circuit board.

Abstract translation: 本发明的实施例涉及将一个或多个天线或电感线圈并入到半导体封装中。 散热器或金属片被包埋在包装中并冲压或以其它方式图案化成螺旋或蛇形形式。 当连接到与印刷电路板通信的半导体芯片时，该图案使得扩展器能够用作电感器或天线。

公开(公告)号：US09972606B2

公开(公告)日：2018-05-15

申请号：US15604803

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Sebastian T. Ventrone

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/00 ,  H01L29/41 ,  H01L23/495 ,  H01L23/482

CPC classification number: H01L25/0657 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L24/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/50 ,  H01L29/40 ,  H01L29/41 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/50 ,  H01L2224/73261 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06579 ,  H01L2924/15311

Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

公开(公告)号：US20170373024A1

公开(公告)日：2017-12-28

申请号：US15195029

申请日：2016-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Richard S. Graf ,  Ezra D.B. Hall ,  Faraydon Pakbaz ,  Sebastian T. Ventrone

IPC: H01L23/00 ,  G01R31/28 ,  H01L23/495

CPC classification number: H01L23/573 ,  G01R31/2853 ,  G01R31/2896 ,  G01R31/44 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle. A chip is attached to the die attach paddle. The chip includes a surface having an outer boundary and a plurality of bond pads arranged proximate to the outer boundary. A first plurality of wires extend from the outer lead fingers to respective locations on the surface of the chip that are interior of the outer boundary relative to the bond pads. A tamper detection circuit is coupled with the first plurality of wires. A second plurality of wires extend from the inner lead fingers to the bond pads on the chip. The second plurality of wires are located between the lead frame and the first plurality of wires.

公开(公告)号：US20170271309A1

公开(公告)日：2017-09-21

申请号：US15604803

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Sebastian T. Ventrone

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L24/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/50 ,  H01L29/40 ,  H01L29/41 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/50 ,  H01L2224/73261 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06579 ,  H01L2924/15311

Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

公开(公告)号：US09659835B1

公开(公告)日：2017-05-23

申请号：US15094026

申请日：2016-04-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sundeep Mandal

IPC: H01L27/02 ,  H01L23/36 ,  H01L23/367 ,  G06F17/50

CPC classification number: H01L23/3677 ,  G06F17/505 ,  G06F17/5077 ,  G06F2217/80 ,  H01L27/0207

Abstract: A technique for designing an integrated circuit includes placing standard cells across a first surface of a substrate of an integrated circuit (IC) design. At least two unoccupied regions are located across the first surface that do not include standard cells. Aspect ratios for one or more micro fill vias that can be placed in the at least two unoccupied regions are determined. The one or more micro fill vias are placed in the at least two unoccupied regions. Finally, one or more partial thermal vias are placed from a second surface of the integrated circuit, opposite the first surface, to thermally couple the one or more partial thermal vias to the one or more micro fill vias to create thermal paths from the first surface to the second surface.

公开(公告)号：US09496234B1

公开(公告)日：2016-11-15

申请号：US14741802

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Kibby B. Horsford ,  Sudeep Mandal

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03828 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/1339 ,  H01L2224/13444 ,  H01L2224/13455 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/381 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2224/11334 ,  H01L2224/023 ,  H01L2224/03

Abstract: An integrated conductive polymer-solder ball structure is provided. The integrated conductive polymer-solder ball structure comprises a sputter seed layer applied to a wafer structure, one or more conductive polymer pad structures applied to the sputtered seed layer at locations on the wafer structure where one or more solder ball structures will be formed, an electroplating layer applied to portions of the one or more conductive polymer pad structures where a photoresist layer has been exposed, and a solder ball formed on each of the electroplating layers thereby forming the one or more solder ball structures.

Abstract translation: 提供了一种集成的导电聚合物 - 焊球结构。 集成导电聚合物 - 焊球结构包括施加到晶片结构的溅射籽晶层，在晶片结构上将形成一个或多个焊球结构的位置处施加到溅射种子层的一个或多个导电聚合物垫结构， 电镀层施加到已经暴露光致抗蚀剂层的一个或多个导电聚合物垫结构的部分，以及形成在每个电镀层上的焊球，从而形成一个或多个焊球结构。

公开(公告)号：US09299590B1

公开(公告)日：2016-03-29

申请号：US14743030

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Ezra D. B. Hall ,  Vibhor Jain ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC: H01L21/66 ,  H01L21/48 ,  H01L21/78 ,  H01L21/768 ,  H01L21/56 ,  H01L23/38 ,  H01L23/367

CPC classification number: H01L23/38 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various particular embodiments include a method of forming an integrated circuit (IC) device including: forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and forming at least one semiconductor device over the donor silicon wafer side of the donor wafer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.

Abstract translation: 各种具体实施例包括形成集成电路（IC）装置的方法，包括：基于IC器件中的升高温度区域的已知位置，在处理晶片的上表面上形成至少一个热电冷却装置; 在覆盖所述热电冷却装置的所述处理晶片上形成第一氧化物层; 在供体硅晶片上形成第二氧化物层以形成施主晶片; 在第一氧化物层和第二氧化物层处将施主晶片接合到处理晶片，使得第二氧化物层接触处理晶片上的第一氧化物层; 以及在施主晶片的供体硅晶片侧上形成至少一个半导体器件，其中所述至少一个热电冷却器件位于所述至少一个半导体器件附近。