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    Calibration for DTC fractional frequency synthesis
    14.
    发明授权
    Calibration for DTC fractional frequency synthesis 有权

    公开(公告)号：US12278643B2

    公开(公告)日：2025-04-15

    申请号：US17481827

    申请日：2021-09-22

    Applicant: Intel Corporation

    Inventor： Somnath Kundu ,  Stefano Pellerano ,  Brent R. Carlton

    IPC: H03L7/197 ,  H03L7/091 ,  H03L7/099

    Abstract: A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.

    TECHNOLOGIES FOR HIGH-SPEED INTERFACES FOR CRYOGENIC QUANTUM CONTROL
    16.
    发明公开
    TECHNOLOGIES FOR HIGH-SPEED INTERFACES FOR CRYOGENIC QUANTUM CONTROL 审中-公开

    公开(公告)号：US20230186142A1

    公开(公告)日：2023-06-15

    申请号：US17549154

    申请日：2021-12-13

    Applicant: Intel Corporation

    Inventor： Todor Mladenov ,  JongSeok Park ,  Stefano Pellerano ,  Sushil Subramanian

    IPC: G06N10/80 ,  G06N10/60

    CPC classification number: G06N10/80 ,  G06N10/60 ,  G06N10/40

    Abstract: Technologies for high-speed interfaces for cryogenic quantum control are disclosed. In the illustrative embodiment, a die for quantum/classical interface circuitry includes digital circuitry operating in a first clock domain and analog circuitry operating in a second clock domain. Clock domain crossing circuitry facilitates asynchronous data transfer from the digital circuitry to the analog circuitry. The illustrative clock domain crossing circuitry includes a first asynchronous first-in-first-out (FIFO) queue at the border of the first clock domain. The first asynchronous FIFO queue is connected to a second asynchronous FIFO queue at the border of the second clock domain.

    TECHNOLOGIES FOR IMPEDANCE MATCHING NETWORKS FOR QUBITS
    17.
    发明公开
    TECHNOLOGIES FOR IMPEDANCE MATCHING NETWORKS FOR QUBITS 审中-公开

    公开(公告)号：US20230155573A1

    公开(公告)日：2023-05-18

    申请号：US17528453

    申请日：2021-11-17

    Applicant: Intel Corporation

    Inventor： Stefano Pellerano ,  JongSeok Park ,  Lester F. Lampert ,  Sushil Subramanian ,  Thomas F. Watson

    IPC: H03H11/28

    CPC classification number: H03H11/28

    Abstract: Technologies for impedance matching networks for qubits are disclosed. In one illustrative embodiment, an impedance matching network matches a 50 Ohm transmission line to a spin qubit with a state-dependent resistance of 100 kiloohms to 105 kiloohms. The illustrative impedance matching network is tunable, allowing the impedance transformation ratio to be changed without significantly changing the matching frequency of the impedance matching network. In some embodiments, the impedance matching network matches a 50 Ohm transmission line to a lower-resistance state of a qubit. In other embodiments, the impedance matching network matches a 50 Ohm transmission line to an impedance value in between a lower-resistance state and a higher-resistance state of a qubit.

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