公开(公告)号：US20150333025A1

公开(公告)日：2015-11-19

申请号：US14277832

申请日：2014-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Eric D. Perfecto ,  Wolfgang Sauter ,  Thomas A. Wassick

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/13017 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/1369 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes.

Abstract translation: 本发明一般而且更具体地涉及制造具有不可润湿侧壁的柱状互连结构的方法以及所得到的结构。 更具体地说，本发明可以包括将柱的侧壁仅暴露于与柱的金属反应的有机材料，以在柱的侧壁上形成有机金属层。 在随后的接合/回流工艺期间，有机金属层可以防止焊料在柱的侧壁上润湿。

公开(公告)号：US09177928B1

公开(公告)日：2015-11-03

申请号：US14260399

申请日：2014-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/1183 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/3841 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012 ,  H01L2224/848 ,  H01L2224/11 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A semiconductor device fabrication method includes forming a barrier layer upon a dielectric layer, forming a pillar interconnect structure upon the barrier layer, forming solder upon the pillar interconnect structure, reflowing the solder to release solder voids, forming a perimeter material around at least a portion of an exposed sidewall of the pillar, and removing the barrier layer exterior to the pillar interconnect structure. Another fabrication method includes forming the barrier layer, forming the pillar interconnect structure, forming the solder upon the pillar interconnect structure, forming a perimeter material on exposed surfaces of the pillar interconnect structure, and removing the barrier layer on the surface of the dielectric layer exterior to the pillar interconnect structure. Another fabrication method includes forming the barrier layer, forming the pillar interconnect structure, forming a wettable material on sidewalls of the pillar, and removing the barrier layer exterior to the pillar interconnect structure.

Abstract translation: 一种半导体器件的制造方法包括在电介质层上形成阻挡层，在阻挡层上形成柱互连结构，在柱互连结构上形成焊料，回流焊料以释放焊料空隙，在周围至少部分形成周边材料 的柱的暴露的侧壁，并且去除柱互连结构外部的阻挡层。 另一种制造方法包括形成阻挡层，形成柱互连结构，在柱互连结构上形成焊料，在柱互连结构的暴露表面上形成周边材料，以及去除电介质层外表面上的阻挡层 到柱互连结构。 另一种制造方法包括形成阻挡层，形成柱互连结构，在柱的侧壁上形成可湿性材料，以及除去柱互连结构外部的阻挡层。

公开(公告)号：US20150311170A1

公开(公告)日：2015-10-29

申请号：US14260399

申请日：2014-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11823 ,  H01L2224/1183 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/3841 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012 ,  H01L2224/848 ,  H01L2224/11 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A semiconductor device fabrication method includes forming a barrier layer upon a dielectric layer, forming a pillar interconnect structure upon the barrier layer, forming solder upon the pillar interconnect structure, reflowing the solder to release solder voids, forming a perimeter material around at least a portion of an exposed sidewall of the pillar, and removing the barrier layer exterior to the pillar interconnect structure. Another fabrication method includes forming the barrier layer, forming the pillar interconnect structure, forming the solder upon the pillar interconnect structure, forming a perimeter material on exposed surfaces of the pillar interconnect structure, and removing the barrier layer on the surface of the dielectric layer exterior to the pillar interconnect structure. Another fabrication method includes forming the barrier layer, forming the pillar interconnect structure, forming a wettable material on sidewalls of the pillar, and removing the barrier layer exterior to the pillar interconnect structure.

Abstract translation: 一种半导体器件的制造方法包括在电介质层上形成阻挡层，在阻挡层上形成柱互连结构，在柱互连结构上形成焊料，回流焊料以释放焊料空隙，在周围至少部分形成周边材料 的柱的暴露的侧壁，并且去除柱互连结构外部的阻挡层。 另一种制造方法包括形成阻挡层，形成柱互连结构，在柱互连结构上形成焊料，在柱互连结构的暴露表面上形成周边材料，以及去除电介质层外表面上的阻挡层 到柱互连结构。 另一种制造方法包括形成阻挡层，形成柱互连结构，在柱的侧壁上形成可湿性材料，以及除去柱互连结构外部的阻挡层。

公开(公告)号：US09728440B2

公开(公告)日：2017-08-08

申请号：US14525267

申请日：2014-10-28

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Harry D. Cox ,  Brian M. Erwin ,  Jorge A. Lubguban ,  Eric D. Perfecto ,  Jennifer D. Schuler

IPC: B32B41/00 ,  H01L21/683 ,  B32B9/04 ,  B32B17/06 ,  B32B7/12 ,  B32B7/06 ,  H01L21/66

CPC classification number: H01L21/6835 ,  B32B7/06 ,  B32B7/12 ,  B32B9/04 ,  B32B17/06 ,  B32B2457/14 ,  H01L22/12 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.

公开(公告)号：US08910853B2

公开(公告)日：2014-12-16

申请号：US13932070

申请日：2013-07-01

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Alexandre Blander ,  Peter J. Brofman ,  Donald W. Henderson ,  Gareth G. Hougham ,  Hsichang Liu ,  Eric D. Perfecto ,  Srinivasa S.N. Reddy ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof ,  Julien Sylvestre ,  Renee L. Weisman

IPC: B23K31/02 ,  H01L21/44 ,  B23K35/36 ,  C22C13/00 ,  B23K35/02 ,  B23K35/26 ,  H01L23/498 ,  H01B13/00 ,  H01B1/02 ,  H05K3/34 ,  B82Y30/00

CPC classification number: H01B1/02 ,  B23K35/0244 ,  B23K35/262 ,  B23K35/36 ,  B23K35/3602 ,  B82Y30/00 ,  C22C13/00 ,  H01B13/00 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0209 ,  H05K2201/0257 ,  Y10T29/49117 ,  H01L2924/00

Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Abstract translation: 在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。 惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。 在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。 添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。

公开(公告)号：US20140339699A1

公开(公告)日：2014-11-20

申请号：US14447908

申请日：2014-07-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Minhua Lu ,  Eric D. Perfecto ,  David J. Russell ,  Wolfgang Sauter ,  Krystyna W. Semkow ,  Thomas A. Wassick

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49816 ,  H01L21/76843 ,  H01L21/76885 ,  H01L23/49866 ,  H01L2224/11 ,  H05K1/09 ,  H05K3/3478 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0344 ,  H05K2201/09745 ,  H05K2203/041

Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.

Abstract translation: 一种互连结构，其包括其中存在电气部件的基板以及与接触焊盘接触的凸起下冶金（UBM）堆叠，所述凸块冶金（UBM）堆叠存在于所述基板中的所述电气部件。 UBM堆叠包括与接触焊盘直接接触电气部件的金属粘合层，与金属粘附层层直接接触的铜（Cu）种子层，第一镍（Ni）阻挡层， 存在于铜（Cu）种子层的直接接触中，以及存在于第一镍（Ni）阻挡层上的至少一个铜（Cu）导体层和至少一个第二镍（Ni）阻挡层的层状结构。 第二镍（Ni）阻挡层上可能存在焊球。

公开(公告)号：US20140319522A1

公开(公告)日：2014-10-30

申请号：US13870026

申请日：2013-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Karen P. McLaughlin ,  Ekta Misra ,  Christopher D. Muzzy ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/11914 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s).

Abstract translation: 公开了半导体晶片处理期间的金属化方法和所得到的结构。 在该方法中，钝化层被图案化，其中第一开口在上方对齐并垂直延伸到下面的金属结构。 形成掩模层并用第一开口对准的第二开口进行图案化，从而形成垂直延伸穿过掩模层和钝化层到下面的金属结构的两层开口。 电沉积工艺在双层开口中形成凸点下焊盘和附加的金属部件，其不同于凸块下焊盘（例如，引线焊盘;最终垂直的） 裂缝结构部分和/或探针垫）。 每个凸点下焊盘和附加的金属特征最初包括铜上的金属盖层。 除去掩模层，形成另外的掩模层并用仅暴露凸块下焊盘的第三开口图案化，并且将焊料材料沉积在凸块下焊盘上。

公开(公告)号：US09190376B1

公开(公告)日：2015-11-17

申请号：US14277832

申请日：2014-05-15

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Eric D. Perfecto ,  Wolfgang Sauter ,  Thomas A. Wassick

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/13017 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/1369 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes.

Abstract translation: 本发明一般而且更具体地涉及制造具有不可润湿侧壁的柱状互连结构的方法以及所得到的结构。 更具体地说，本发明可以包括将柱的侧壁仅暴露于与柱的金属反应的有机材料，以在柱的侧壁上形成有机金属层。 在随后的接合/回流工艺期间，有机金属层可以防止焊料在柱的侧壁上润湿。