公开(公告)号：US09761514B2

公开(公告)日：2017-09-12

申请号：US15205223

申请日：2016-07-08

申请人： Intel Corporation

发明人： Qing Ma ,  Chuan Hu ,  Patrick Morrow

IPC分类号： H05K1/11 ,  H01L23/498 ,  H05K3/42 ,  H05K3/46 ,  H01L21/48 ,  H01L23/367 ,  H01L23/00

CPC分类号： H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

摘要： Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

公开(公告)号：US09543197B2

公开(公告)日：2017-01-10

申请号：US13719836

申请日：2012-12-19

申请人： INTEL CORPORATION

发明人： Chuan Hu ,  Dingying Xu ,  Yoshihiro Tomita

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27002 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/2784 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及具有通过界面层连接到集成电路基板的一个或多个管芯的集成电路（IC）封装的技术和配置。 在一个实施例中，界面层可以包括各向异性部分，其被配置为在诸如管芯和集成电路基板的一个或多个部件之间的面外方向上传导电信号。 在另一个实施例中，界面层可以是介电层或电绝缘层。 在另一个实施例中，界面层可以包括用作两个部件之间的互连的各向异性部分，电介质或绝缘部分，以及由电介质或绝缘部分包围并用作相互之间的互连的一个或多个互连结构 或其他组件。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150187727A1

公开(公告)日：2015-07-02

申请号：US14643329

申请日：2015-03-10

申请人： INTEL CORPORATION

发明人： Chuan Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K1/181 ,  H01L2924/01083 ,  H01L2924/00014

摘要： The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

摘要翻译： 本公开涉及制造微电子封装的领域，其中在沉积在第一基板上的电介质层中形成空腔以保持焊接互连之间的分离。 在一个实施例中，空腔可以具有倾斜的侧壁。 在另一个实施例中，焊膏可以沉积在空腔中，并且在加热时可以形成焊料结构。 在其它实施例中，焊料结构可以放置在空腔中，或者可以形成在可以连接第一衬底的第二衬底上。 在其它实施例中，可以在第一基板和第二基板上形成焊料结构。 焊料结构可以用于通过与第二衬底上的接触焊盘或焊料结构的接触和回流来形成焊料互连。

公开(公告)号：US10468367B2

公开(公告)日：2019-11-05

申请号：US15884167

申请日：2018-01-30

申请人： INTEL CORPORATION

发明人： Chuan Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC分类号： H01L23/00 ,  H05K1/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

摘要： The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

公开(公告)号：US09942980B2

公开(公告)日：2018-04-10

申请号：US15123215

申请日：2014-05-28

申请人： INTEL CORPORATION

发明人： Chuan Hu ,  Adel A. Elsherbini ,  Yoshihiro Tomita ,  Shawna Liff

IPC分类号： H01L23/538 ,  H05K1/02 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18

CPC分类号： H05K1/0283 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/1515 ,  H01L2924/181 ,  H05K1/036 ,  H05K1/185 ,  H05K3/1275 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09263 ,  H05K2201/10151 ,  H01L2924/00012

摘要： Embodiments of the present disclosure describe a wavy interconnect for bendable and stretchable devices and associated techniques and configurations. In one embodiment, an interconnect assembly includes a flexible substrate defining a plane and a wavy interconnect disposed on the flexible substrate and configured to route electrical signals of an integrated circuit (IC) device in a first direction that is coplanar with the plane, the wavy interconnect having a wavy profile from a second direction that is perpendicular to the first direction and coplanar with the plane. Other embodiments may be described and/or claimed.

公开(公告)号：US09848490B2

公开(公告)日：2017-12-19

申请号：US14269571

申请日：2014-05-05

申请人： Intel Corporation

发明人： Chuan Hu

IPC分类号： H01L21/44 ,  H01L23/52 ,  H05K1/02 ,  B23K1/00 ,  B23K1/20 ,  B23K3/06 ,  H01L23/00 ,  H05K1/11 ,  H05K13/04 ,  B23K101/40

CPC分类号： H05K1/0271 ,  B23K1/0018 ,  B23K1/203 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05647 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/11442 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3841 ,  H05K1/11 ,  H05K13/0465 ,  H05K2201/10734 ,  Y10T428/12222 ,  H01L2924/00014 ,  H01L2924/00

摘要： An interconnection technology may use molded solder to define solder balls. A mask layer may be patterned to form cavities and solder paste deposited in the cavities. Upon heating, solder balls are formed. The cavity is defined by spaced walls to keep the solder ball from bridging during a bonding process. In some embodiments, the solder bumps connected to the solder balls may have facing surfaces which are larger than the facing surfaces of the solder ball.

公开(公告)号：US09673131B2

公开(公告)日：2017-06-06

申请号：US13859659

申请日：2013-04-09

申请人： Intel Corporation

发明人： Chuan Hu ,  Qing Ma ,  Chia-Pin Chiu

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L23/481 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for integrated circuit package assemblies including a glass solder mask layer and/or bridge. In one embodiment, an apparatus includes one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the solder mask layer being coupled with the one or more build-up layers and having openings disposed in the solder mask layer to allow coupling of package-level interconnect structures with the electrical routing features through the one or more openings. Other embodiments may be described and/or claimed.

公开(公告)号：US20160322290A1

公开(公告)日：2016-11-03

申请号：US15205223

申请日：2016-07-08

申请人： Intel Corporation

发明人： Qing Ma ,  Chuan Hu ,  Patrick Morrow

IPC分类号： H01L23/498 ,  H01L23/367 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

摘要： Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

摘要翻译： 公开了用于集成电路（IC）装置的基板的实施例。 衬底包括由已经结合在一起的两个或更多个离散的玻璃层组成的芯。 可以在相邻的玻璃层之间设置单独的粘合层，以将这些层连接在一起。 衬底还可以包括在多层玻璃芯的相对侧上或者可能在芯的一侧上的堆积结构。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸通过多层玻璃芯，并且一个或多个导体可以与布置在芯上的积聚结构电耦合。 描述和要求保护其他实施例。

公开(公告)号：US10535634B2

公开(公告)日：2020-01-14

申请号：US15106761

申请日：2015-07-22

申请人： INTEL CORPORATION

发明人： Vijay K. Nair ,  Chuan Hu ,  Thorsten Meyer

IPC分类号： H01L23/04 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

摘要： Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.

公开(公告)号：US10122089B2

公开(公告)日：2018-11-06

申请号：US15206428

申请日：2016-07-11

申请人： Intel Corporation

发明人： Vijay K. Nair ,  Chuan Hu ,  Shawna M. Liff ,  Larry E. Mosley

IPC分类号： H01Q7/00 ,  H01Q7/06 ,  H01Q1/22 ,  G06F1/16 ,  H01F1/00 ,  H01Q23/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/66 ,  H01L23/31

摘要： A method apparatus and material are described for radio frequency passives and antennas. In one example, an electronic component has a synthesized magnetic nanocomposite material with aligned magnetic domains, a conductor embedded within the nanocomposite material, and contact pads extending through the nanocomposite material to connect to the conductor.