公开(公告)号：US20160204252A1

公开(公告)日：2016-07-14

申请号：US15073574

申请日：2016-03-17

Applicant: Renesas Electronics Corporation

Inventor： Koujirou MATSUI ,  Takehiko SAKAMOTO ,  Kazuyuki UMEZU ,  Tomoaki UNO

IPC: H01L29/78 ,  H01L23/528 ,  H03K17/687

CPC classification number: H01L23/528 ,  H01L23/4824 ,  H01L23/53214 ,  H01L23/53228 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7835 ,  H01L2224/16225 ,  H01L2924/19105 ,  H03K17/687

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

公开(公告)号：US20160043042A1

公开(公告)日：2016-02-11

申请号：US14919597

申请日：2015-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuhiko FUNATSU ,  Yukihiro SATO ,  Yuichi YATO ,  Tomoaki UNO

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/564 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.

公开(公告)号：US20150137260A1

公开(公告)日：2015-05-21

申请号：US14470745

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Koujirou MATSUI ,  Takehiko SAKAMOTO ,  Kazuyuki UMEZU ,  Tomoaki UNO

IPC: H01L23/528 ,  H01L23/532 ,  H01L27/088

CPC classification number: H01L23/528 ,  H01L23/4824 ,  H01L23/53214 ,  H01L23/53228 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7835 ,  H01L2224/16225 ,  H01L2924/19105 ,  H03K17/687

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Abstract translation: 在半导体衬底的主表面上的LDMOSFET形成区域中形成多个并联连接以构成功率MISFET的单位MISFET元件。 控制电源MISFET的栅极电压的控制电路形成在半导体衬底的主表面上的驱动电路区域中。 在半导体衬底上形成具有由相同金属材料制成的多个布线层的布线结构。 形成在LDMOSFET形成区域中的多个单位MISFET元件的栅电极通过形成在由同一金属材料制成的多个布线层的全部中的栅极布线彼此电连接。

公开(公告)号：US20130147064A1

公开(公告)日：2013-06-13

申请号：US13764336

申请日：2013-02-11

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATO ,  Tomoaki UNO

IPC: H01L23/492

CPC classification number: H01L23/492 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H02M7/003 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The reliability of a semiconductor device is improved.A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Abstract translation: 提高了半导体器件的可靠性。 半导体器件的封装在内部包括形成功率MOSFET的第一半导体芯片和第二半导体芯片以及形成控制第一和第二半导体芯片的控制电路的第三半导体芯片。 第一至第三半导体芯片分别安装在芯片焊盘上。 第一半导体芯片的高侧的源电极接合焊盘通过金属板与管芯焊盘的第一管芯焊盘电连接。 在芯片焊盘7D2的顶面设置有形成在安装有第二半导体芯片的区域中的镀层和形成在金属板接合的区域中的另一个镀层，并且将镀层彼此分离，并且用 在其间不形成镀层的区域。

公开(公告)号：US20160233204A1

公开(公告)日：2016-08-11

申请号：US15133032

申请日：2016-04-19

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko FUNATSU ,  Tomoaki UNO ,  Toru UEGURI ,  Yukihiro SATO

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L25/50 ,  H01L21/4835 ,  H01L21/4839 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the leadframe, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

Abstract translation: 为了提高将带施加到基板的后表面上的带的可靠性，同时确保施加到基板的后表面的带的耐热性。 在支撑构件中设置的沟槽的底表面和驱动器IC芯片的上表面之间存在间隙。 另一方面，引线框架的上表面侧由支撑构件支撑，使得沟槽的底表面接触安装在低MOS芯片上的低MOS片的上表面。 因此，即使在驱动IC芯片和Low-MOS芯片安装在引线框架的上表面侧的状态下，也可以将带子可靠地施加到引线框架的后表面（特别是到后表面 的产品区域）。

公开(公告)号：US20160005854A1

公开(公告)日：2016-01-07

申请号：US14857596

申请日：2015-09-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

IPC: H01L29/78 ,  H02M7/00

CPC classification number: H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract translation: 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基 与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

公开(公告)号：US20140312510A1

公开(公告)日：2014-10-23

申请号：US14322320

申请日：2014-07-02

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATOU ,  Tomoaki UNO ,  Nobuyoshi MATSUURA ,  Masaki SHIRAISHI

IPC: H01L23/538

CPC classification number: H01L23/5386 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/165 ,  H01L29/4175 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/1588 ,  H05K7/02 ,  Y02B70/1466 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/2075 ,  H01L2924/20754

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Abstract translation: 本发明提供一种具有电路的非绝缘型DC-DC转换器，其中用于高侧开关的功率MOS•FET和低边开关的功率MOS•FET串联连接。 在非绝缘型DC-DC转换器中，用于高侧开关的功率晶体管，低边开关的功率晶体管和驱动它们的驱动电路分别由不同的半导体芯片构成。 三个半导体芯片被容纳在一个封装中，并且包括用于高侧开关的功率晶体管的半导体芯片和包括驱动电路的半导体芯片被布置成彼此接近。

公开(公告)号：US20130207256A1

公开(公告)日：2013-08-15

申请号：US13754245

申请日：2013-01-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoaki UNO ,  Tetsuya KAWASHIMA

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L21/823475 ,  H01L23/34 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L27/088 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01015 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing.A semiconductor device has a structure formed by covering a principal surface of a semiconductor chip having the principal surface and a plurality of MIS type FETs formed over the principal surface with a plurality of metal plate wires having pectinate shapes; allocating the pectinate parts alternately in a planar view over the principal surface; and further electrically coupling the plural metal plate wires to a plurality of terminals.

Abstract translation: 用于诸如DC / DC转换器的电源电路的常规半导体器件具有散热和小型化的问题，特别是在尺寸减小的情况下具有散热等问题。 半导体器件具有通过覆盖具有主表面的半导体芯片的主表面和在主表面上形成的多个MIS型FET的多个具有果胶形状的金属板线而形成的结构; 在主表面上的平面视图中交替地分配果胶部分; 并且还将多个金属板电线进一步电耦合到多个端子。

公开(公告)号：US20130203217A1

公开(公告)日：2013-08-08

申请号：US13717464

申请日：2012-12-17

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATOU ,  Tomoaki UNO ,  Nobuyoshi MATSUURA ,  Masaki SHIRAISHI

IPC: H01L23/00

CPC classification number: H01L23/5386 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/165 ,  H01L29/4175 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/1588 ,  H05K7/02 ,  Y02B70/1466 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/2075 ,  H01L2924/20754

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Abstract translation: 本发明提供一种具有电路的非绝缘型DC-DC转换器，其中用于高侧开关的功率MOS.FET和用于低侧开关的功率MOS.FET串联连接。 在非绝缘型DC-DC转换器中，用于高侧开关的功率晶体管，低边开关的功率晶体管和驱动它们的驱动电路分别由不同的半导体芯片构成。 三个半导体芯片被容纳在一个封装中，并且包括用于高侧开关的功率晶体管的半导体芯片和包括驱动电路的半导体芯片被布置成彼此接近。